Patents by Inventor Troy R. Sorensen

Troy R. Sorensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230077163
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Application
    Filed: October 27, 2022
    Publication date: March 9, 2023
    Inventors: Troy R. Sorensen, Mohd Kamran Akhtar
  • Patent number: 11508742
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Troy R. Sorensen, Mohd Kamran Akhtar
  • Publication number: 20200118919
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Application
    Filed: November 7, 2019
    Publication date: April 16, 2020
    Inventors: Troy R. Sorensen, Mohd Kamran Akhtar
  • Patent number: 10504838
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Troy R. Sorensen
  • Publication number: 20180082940
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Application
    Filed: September 21, 2016
    Publication date: March 22, 2018
    Inventors: Troy R. Sorensen, Mohd Kamran Akhtar
  • Patent number: 9385132
    Abstract: A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array. The etch mask is used while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings. Individual recessed access gate constructions are formed in the individual recessed access device trenches. Other methods are contemplated, including arrays of recessed access devices independent of method of manufacture.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Lars P. Heineck, Troy R. Sorensen
  • Publication number: 20130049072
    Abstract: A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array. The etch mask is used while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings. Individual recessed access gate constructions are formed in the individual recessed access device trenches. Other methods are contemplated, including arrays of recessed access devices independent of method of manufacture.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Lars P. Heineck, Troy R. Sorensen
  • Patent number: 6749715
    Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: June 15, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Terry L. Gilton, Troy R. Sorensen
  • Patent number: 6602795
    Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: August 5, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Terry L. Gilton, Troy R. Sorensen
  • Patent number: 6519031
    Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: February 11, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Terry L. Gilton, Troy R. Sorensen
  • Publication number: 20020182883
    Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.
    Type: Application
    Filed: July 15, 2002
    Publication date: December 5, 2002
    Inventors: Terry L. Gilton, Troy R. Sorensen
  • Patent number: 6420275
    Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: July 16, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Terry L. Gilton, Troy R. Sorensen
  • Publication number: 20020004312
    Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.
    Type: Application
    Filed: August 22, 2001
    Publication date: January 10, 2002
    Inventors: Terry L. Gilton, Troy R. Sorensen
  • Publication number: 20010023130
    Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.
    Type: Application
    Filed: May 24, 2001
    Publication date: September 20, 2001
    Inventors: Terry L. Gilton, Troy R. Sorensen