Abstract: A prefetch circuit for use with a memory including a storage register for receiving a command from the memory, a decoding circuit for decoding the command to determine the identification of an index register contained within the command, and a fetch circuit for fetching the contents of the index register from the command. The prefetch circuit also includes a virtual address storage register for receiving and storing the virtual address of the command, an adding circuit for adding a predetermined offset to the virtual address of the command to obtain a new virtual address, a comparison circuit for determining if the new virtual address from the adding circuit has crossed a virtual page boundary, a transfer circuit responsive to the comparison circuit for transferring the real address in the real address storage register to the adding circuit for adding the offset thereto, thereby obtaining a new real address. The fetch circuit then fetches a prefetched command from the memory at the new real address.