Patents by Inventor Truls Lowgren
Truls Lowgren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200286604Abstract: A method is disclosed for generating a database to be used to set illumination of an adjustable light source. The method comprising: for a plurality of different users: identifying an individual user; setting a specific light profile of the adjustable light source, the specific light profile comprising information pertaining to a spectral content and/or intensity of light by which the individual user is exposed to; while exposing the individual user for the specific light profile, sensing data pertaining to a health condition and/or a behavior of the individual user; determining a data set linking the specific light profile, genomic data pertaining to the individual user, and the data pertaining to the health condition and/or the behavior of the individual user sensed while exposing the individual user to the specific light profile; and storing the linked data set in a database. A light control system is further provided.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Inventors: Tord WINGREN, Truls LÖWGREN
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Patent number: 9419183Abstract: An opto-electric structure includes a plurality of nano elements arranged side by side on a support layer, where each nano element includes at least a first conductivity type semiconductor nano sized core, and where the core and a second conductivity type semiconductor form a pn or pin junction. A first electrode layer that extends over the plurality of nano elements and is in electrical contact with at least a portion of the second conductivity type semiconductor, and a mirror provided on a second conductivity type semiconductor side of the structure.Type: GrantFiled: December 16, 2014Date of Patent: August 16, 2016Assignee: GLO ABInventors: Truls Lowgren, Ghulam Hasnain
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Patent number: 9312442Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.Type: GrantFiled: August 18, 2015Date of Patent: April 12, 2016Assignee: GLO ABInventor: Truls Lowgren
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Publication number: 20150357520Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventor: Truls Lowgren
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Patent number: 9117990Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.Type: GrantFiled: January 28, 2014Date of Patent: August 25, 2015Assignee: GLO ABInventor: Truls Lowgren
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Patent number: 9096429Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.Type: GrantFiled: July 3, 2014Date of Patent: August 4, 2015Assignee: QUNANO ABInventors: Lars Ivar Samuelson, Patrik Svensson, Jonas Ohlsson, Truls Lowgren
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Publication number: 20150207037Abstract: An opto-electric structure includes a plurality of nano elements arranged side by side on a support layer, where each nano element includes at least a first conductivity type semiconductor nano sized core, and where the core and a second conductivity type semiconductor form a pn or pin junction. A first electrode layer that extends over the plurality of nano elements and is in electrical contact with at least a portion of the second conductivity type semiconductor, and a mirror provided on a second conductivity type semiconductor side of the structure.Type: ApplicationFiled: December 16, 2014Publication date: July 23, 2015Inventors: Truls Lowgren, Ghulam Hasnain
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Patent number: 9087896Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: GrantFiled: October 8, 2013Date of Patent: July 21, 2015Assignee: QUNANO ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Lowgren
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Patent number: 8937295Abstract: An opto-electric structure includes a plurality of nano elements arranged side by side on a support layer, where each nano element includes at least a first conductivity type semiconductor nano sized core, and where the core and a second conductivity type semiconductor form a pn or pin junction. A first electrode layer that extends over the plurality of nano elements and is in electrical contact with at least a portion of the second conductivity type semiconductor, and a mirror provided on a second conductivity type semiconductor side of the structure.Type: GrantFiled: December 6, 2012Date of Patent: January 20, 2015Assignee: GLO ABInventors: Truls Lowgren, Ghulam Hasnain
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Publication number: 20140312381Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.Type: ApplicationFiled: July 3, 2014Publication date: October 23, 2014Inventors: Lars Ivar Samuelson, Patrik Svensson, Jonas Ohlsson, Truls Lowgren
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Patent number: 8796119Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.Type: GrantFiled: May 3, 2013Date of Patent: August 5, 2014Assignee: Qunano ABInventors: Lars Ivar Samuelson, Patrik Svensson, Jonas Ohlsson, Truls Lowgren
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Publication number: 20140141555Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: GLO ABInventor: Truls Lowgren
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Publication number: 20140103423Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: ApplicationFiled: October 8, 2013Publication date: April 17, 2014Applicant: QUNANO ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Lowgren
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Patent number: 8669125Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.Type: GrantFiled: June 17, 2011Date of Patent: March 11, 2014Assignee: GLO ABInventor: Truls Löwgren
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Patent number: 8551834Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: GrantFiled: April 27, 2012Date of Patent: October 8, 2013Assignee: QuNano ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Lowgren
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Patent number: 8455857Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.Type: GrantFiled: September 8, 2011Date of Patent: June 4, 2013Assignee: QuNano ABInventors: Lars Ivar Samuelson, Patrik Svensson, Jonas Ohlsson, Truls Lowgren
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Patent number: 8350251Abstract: An opto-electric structure includes a plurality of nano elements arranged side by side on a support layer, where each nano element includes at least a first conductivity type semiconductor nano sized core, and where the core and a second conductivity type semiconductor form a pn or pin junction. A first electrode layer that extends over the plurality of nano elements and is in electrical contact with at least a portion of the second conductivity type semiconductor, and a mirror provided on a second conductivity type semiconductor side of the structure.Type: GrantFiled: October 3, 2011Date of Patent: January 8, 2013Assignee: GLO ABInventors: Truls Lowgren, Ghulam Hasnain
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Publication number: 20120211727Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: ApplicationFiled: April 27, 2012Publication date: August 23, 2012Applicant: QuNano ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Löwgren
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Patent number: 8178403Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: GrantFiled: September 18, 2007Date of Patent: May 15, 2012Assignee: QuNano ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Löwgren
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Publication number: 20110316019Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.Type: ApplicationFiled: September 8, 2011Publication date: December 29, 2011Inventors: Lars Ivar SAMUELSON, Patrik SVENSSON, Jonas OHLSSON, Truls LOWGREN