Patents by Inventor Trung D. Nguyen
Trung D. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10705962Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.Type: GrantFiled: December 21, 2017Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Carl J. Beckmann, Robert G. Blankenship, Chyi-Chang Miao, Chitra Natarajan, Anthony-Trung D. Nguyen
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Publication number: 20190196968Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Carl J. Beckmann, Robert G. Blankenship, Chyi-Chang Miao, Chitra Natarajan, Anthony-Trung D. Nguyen
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Patent number: 9069671Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: GrantFiled: July 21, 2014Date of Patent: June 30, 2015Assignee: Intel CorporationInventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Publication number: 20140337580Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: ApplicationFiled: July 21, 2014Publication date: November 13, 2014Inventors: CHRISTOPHER J. HUGHES, YEN-KUANG CHEN, CHANGKYU KIM, DAEHYUN KIM, VICTOR W. LEE, ANTHONY-TRUNG D. NGUYEN, NADATHUR RAJAGOPALAN SATISH
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Patent number: 8799577Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: GrantFiled: July 2, 2013Date of Patent: August 5, 2014Assignee: Intel CorporationInventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Publication number: 20130297878Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: ApplicationFiled: July 2, 2013Publication date: November 7, 2013Inventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Patent number: 8478941Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: GrantFiled: July 24, 2012Date of Patent: July 2, 2013Assignee: Intel CorporationInventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Patent number: 8463820Abstract: In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed.Type: GrantFiled: May 26, 2009Date of Patent: June 11, 2013Assignee: Intel CorporationInventors: Jatin Chhugani, Sanjeev Kumar, Anthony-Trung D. Nguyen, Yen-Kuang Chen, Victor W. Lee, William Macy
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Publication number: 20120290799Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: ApplicationFiled: July 24, 2012Publication date: November 15, 2012Inventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Patent number: 8230172Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: GrantFiled: December 3, 2009Date of Patent: July 24, 2012Assignee: Intel CorporationInventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Patent number: 8151012Abstract: Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.Type: GrantFiled: September 25, 2009Date of Patent: April 3, 2012Assignee: Intel CorporationInventors: Changkyu Kim, Albert Lin, Christopher J. Hughes, Anthony-Trung D. Nguyen, Yen-Kuang Chen, Zeshan A. Chishti, Bryan K. Casper
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Publication number: 20110161060Abstract: A method of computing a collision-free velocity (117, 217) for an agent (110) in a crowd simulation environment (100) comprises identifying a quadratic optimization problem that corresponds to the collision-free velocity, and finding an exact solution for the quadratic optimization problem by using a geometric approach.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Inventors: Changkyu Kim, Stephen J. Guy, Anthony-Trung D. Nguyen, Daehyun Kim, Jatin Chhugani
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Publication number: 20110138122Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.Type: ApplicationFiled: December 3, 2009Publication date: June 9, 2011Inventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
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Publication number: 20110078340Abstract: Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: CHANGKYU KIM, Albert Lin, Christopher J. Hughes, Anthony-Trung D. Nguyen, Yen-Kuang Chen, Zeshan A. Chishti, Bryan K. Casper
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Publication number: 20110066806Abstract: In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed.Type: ApplicationFiled: May 26, 2009Publication date: March 17, 2011Inventors: Jatin Chhugani, Sanjeev Kumar, Anthony-Trung D. Nguyen, Yen-Kuang Chen, Victor W. Lee, William Macy
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Patent number: 7500793Abstract: A glass-to-meal seal for use in high temperature and high pressure environments is described. The glass-to-metal seals includes an optical fiber having a metallized portion, the metallized portion having an outer dimension; an object having a high strength, corrosion-resistant alloy, the object having an outer surface and an inner surface defining a bore, the bore having a dimension larger than the outer dimension of the metallized portion of the optical fiber; and a hardened solder material disposed between the metallized portion of the optical fiber and the inner surface of the bore, such that a hermetic seal is provided between the metallized portion of the optical fiber and the inner surface of the bore; wherein the solder includes a substance having a melting temperature greater than about 250° C.Type: GrantFiled: May 30, 2006Date of Patent: March 10, 2009Assignee: Greene, Tweed of Delaware, Inc.Inventors: Pragna Subhash Patel, Trung D. Nguyen, Charles Pence Burke, George Frank DeNardo, Jr.
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Patent number: 6036424Abstract: A cart for unloading and transporting chain is provided. The cart includes a frame with a number of tracks of a predetermined configuration which are superimposed over one another. Long segments of chain are routed from an oven onto a transfer rail assembly which, in turn, routes the segment of chain to a given track mounted in the cart. Subsequent segments are similarly routed to other tracks in the cart after the cart is elevated to register the empty track to be loaded with the corresponding transfer rail. As a result, the unloading and transporting chain for rebuild and repair is significantly simplified while reducing the overall time and burden associated therewith.Type: GrantFiled: August 12, 1998Date of Patent: March 14, 2000Assignee: Toray Plastics (America), Inc.Inventors: Scott J. Santangelo, Trung D. Nguyen, John H Klose
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Patent number: 5995956Abstract: A questionless case-based knowledge base suitable for access by an intelligent search engine and an associated method for constructing the same from pre-existing on-line documentation. A case structure for questionless cases is determined. The determined case structure includes a first field for containing a title for a case, a second field for containing a description of the case and a third field for containing a solution for the case. On-line documentation having information directed to a plurality of topics, each of which includes a title portion and a contents portion, is then provided. The information directed to each of the plurality of topics is then reconfigured into the determined case structure such that the title portion of each topic is configured as a first field of a corresponding case and the contents portion of each topic is configured as a second field of the corresponding case.Type: GrantFiled: August 27, 1997Date of Patent: November 30, 1999Assignee: Compaq Computer CorporationInventor: Trung D. Nguyen
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Patent number: 5720001Abstract: A questionless case-based knowledge base suitable for access by an intelligent search engine and an associated method for constructing the same from pre-existing on-line documentation. A case structure for questionless cases is determined. The determined case structure includes a first field for containing a title for a case, a second field for containing a description of the case and a third field for containing a solution for the case. On-line documentation having information directed to a plurality of topics, each of which includes a title portion and a contents portion, is then provided. The information directed to each of the plurality of topics is then reconfigured into the determined case structure such that the title portion of each topic is configured as a first field of a corresponding case and the contents portion of each topic is configured as a second field of the corresponding case.Type: GrantFiled: May 8, 1995Date of Patent: February 17, 1998Assignee: Compaq Computer CorporationInventor: Trung D. Nguyen
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Patent number: 5701399Abstract: A system in which a case-based search engine is integrated into a "help" database. The help database may be organized in a predetermined manner and converted by a computer program into a case-based format. An operator of a "help" program (e.g., a user who desires on-line help) may request a case-based search of the case-base using case-based methods. The case-based search provides a set of likely cases, i.e., help topics, from among which the operator may select the next help topic to view. The system may also present matched objects in response to the query, may respond to iterative refinement of the query (in similar manner to known iterative case-based methods) and may order matched objects by quality of match.Type: GrantFiled: December 20, 1996Date of Patent: December 23, 1997Assignee: Inference CorporationInventors: S. Daniel Lee, Trung D. Nguyen, Mary P. Czerwinski