Patents by Inventor Tsai-An Yu

Tsai-An Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220208684
    Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Ting-Chin Cho, Igor Elkanovich, Amnon Parnass, Chia-Hsiang Chang, Tsai-Ming Yang, Yen-Chung T. Chen, Ting-Hsu Chien, Yuan-Hung Lin, Chao-Ching Huang, Li-Ya Tseng, Pei Yu, Jia-Liang Chen, Yen-Wei Chen, Chung-Kai Wang, Chun-Hsu Chen, Yu-Ju Chang, Li-Hua Lin, Zanyu Yang
  • Publication number: 20220188433
    Abstract: A computer implemented method for managing the scope of permissions granted by users to application that includes collecting a set of permissions for an application from an application provider publication; and collecting a process flow for functional steps of the application from a review of the application that is published on a product review type publication. The computer implemented method further includes dividing the functional steps of the application into a plurality of journeys, each of said plurality of journeys having a function associated with a stage of a functional step from a perspective of a user; and matching permissions from the set of permissions for each journey of said plurality of journeys to provide matched permissible permissions to journeys stored in a customer journey store.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Hao Chun Hung, Po-Cheng Chiu, Tsai-Hsuan Hsieh, Cheng-Lun Yang, Chiwen Chang, Shin Yu Wey
  • Patent number: 11355544
    Abstract: The present disclosure describes a method for the formation of mirror micro-structures on radiation-sensing regions of image sensor devices. The method includes forming an opening within a front side surface of a substrate; forming a conformal implant layer on bottom and sidewall surfaces of the opening; growing a first epitaxial layer on the bottom and the sidewall surfaces of the opening; depositing a second epitaxial layer on the first epitaxial layer to fill the opening, where the second epitaxial layer forms a radiation-sensing region. The method further includes depositing a stack on exposed surfaces of the second epitaxial layer, where the stack includes alternating pairs of a high-refractive index material layer and a low-refractive index material layer.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Yu Liao, Tsai-Hao Hung, Ying-Hsun Chen
  • Patent number: 11349023
    Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Publication number: 20220155668
    Abstract: A notebook computer including a screen, a body, and a camera module is provided. The body is pivotally connected to the screen so that the screen is opened and closed relative to the body. The camera module is stored in one of the screen and the body and includes a photosensitive element and a first polarizer. The first polarizer is disposed between the screen and the photosensitive element. The screen includes a display panel and a second polarizer. The second polarizer is disposed between the display panel and the first polarizer. The first polarizer and the second polarizer have different polarization directions.
    Type: Application
    Filed: October 19, 2021
    Publication date: May 19, 2022
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Hsin Yeh, Cheng-Hao Hsu, Ting-Hsuan Yu, Han-Tsai Liu, Jyh-Chyang Tzou, Chih-Wen Chiang
  • Publication number: 20220157814
    Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.
    Type: Application
    Filed: December 22, 2020
    Publication date: May 19, 2022
    Inventors: Shi-You Liu, Ming-Shiou Hsieh, Zih-Hsuan Huang, Tsai-Yu Wen, Yu-Ren Wang
  • Publication number: 20220140080
    Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 5, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
  • Publication number: 20220088177
    Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 24, 2022
    Applicant: Immune Design Corp.
    Inventors: Peter Lars Aksel Berglund, Jacob Freeman Archer, Tsai-yu Lin
  • Publication number: 20220093742
    Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.
    Type: Application
    Filed: October 27, 2021
    Publication date: March 24, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • Publication number: 20220093741
    Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.
    Type: Application
    Filed: October 27, 2021
    Publication date: March 24, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • Publication number: 20220084372
    Abstract: A doorbell system includes a power supply circuit, a smart module, a chime, a chime switch and a control module. The smart module provides a smart function. The chime switch is electrically connected between the control module, the smart module, and the power supply circuit. When the chime switch is turned on, the current flows through the chime under control of the control module. When the chime switch is turned off, the current cannot flow through the chime under control of the control module; consequently, the buzzing sound cannot be generated.
    Type: Application
    Filed: October 26, 2020
    Publication date: March 17, 2022
    Inventors: TSAI-YU YU, HUNG-CHEN WU, TENG-CHIEH YANG
  • Patent number: 11271078
    Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: March 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
  • Publication number: 20220054627
    Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.
    Type: Application
    Filed: September 3, 2021
    Publication date: February 24, 2022
    Applicant: Immune Design Corp.
    Inventors: Peter Lars Aksel Berglund, Jacob Freeman Archer, Tsai-yu Lin
  • Patent number: 11195918
    Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • Patent number: 11135283
    Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 5, 2021
    Assignee: Immune Design Corp.
    Inventors: Peter Lars Aksel Berglund, Jacob Freeman Archer, Tsai-Yu Lin
  • Publication number: 20210272816
    Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.
    Type: Application
    Filed: November 18, 2020
    Publication date: September 2, 2021
    Inventors: Chen-Fong Tsai, Ya-Lun Chen, Tsai-Yu Huang, Yahru Cheng, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11107689
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 31, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Tsai-Yu Wen, Ming-Shiou Hsieh, Rong-Sin Lin, Ching-I Li, Neng-Hui Yang
  • Publication number: 20210242334
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.
    Type: Application
    Filed: January 19, 2021
    Publication date: August 5, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Yun LI, Tsai-Yu HUANG, Huicheng CHANG, Yee-Chia YEO
  • Patent number: 10983556
    Abstract: An electronic device including a main body, a handle and a driven mechanism is provided. The main body includes a base and a button unit movably disposed on the base. The handle is movably connected to the main body. The handle is adapted to be rotated from a first position to a second position relative to the main body. The driven mechanism includes a first connection element and an ascending/descending assembly. A first section of the first connection element is fixed to the handle, and a second section of the first connection element is movably disposed in the base. The ascending/descending assembly is disposed in the base and located between the second section and a bottom of the button unit. When the handle is rotated from the first position to the second position, the first connection element moves with the handle, and the ascending/descending assembly is moved with the second section and lifts up the button unit.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 20, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yuan-Ping Chu, Jyh-Chyang Tzou, Tsai-Yu Lin, Chun-Ping Li
  • Patent number: 10980353
    Abstract: A mattress, bed, cushion, or other device to support a user in a pre-determined posture. The mattress, bed, cushion, or other device includes compressible cells configured to inflate based on characteristics of particular contact areas of the user, and contact, in response to inflating based on the characteristics, the user in various contact areas to support the pre-determined posture. In particular, inflating the compressible cells based on characteristics of particular contact areas reduces the risk of the user developing pressure ulcers.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: April 20, 2021
    Assignee: MEDICUSTEK, INC.
    Inventors: Aaron R. Clousing, Chia-Ming Hsu, Tsai-Yu Lin