Abstract: A method for managing a memory apparatus includes: linking a first host address obtained from a received first access command to a first page of a physical block; linking a second host address obtained from a received second access command to at least a second page of the physical block; storing first data of the received first access command and second data of the received second access command into the physical block; building a valid page position table, and storing the valid page position table in a volatile memory; before the pages of the physical block are fully programmed, storing a temporary local page linking address table in the volatile memory; building a global page address linking table according to the linking relationships between the pages of the physical block and the host addresses; and storing the global page address linking table in the volatile memory.

Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.

Abstract: The present invention provides an image sensor module, including an integrated circuit substrate, an image sensing chip, a cover plate and an encapsulating material. The image sensing chip is disposed on the integrated circuit substrate. The image sensing chip includes an image sensing area and a non-image sensing area. A dam is disposed between the cover plate and the non-image sensing area of the image sensing chip. The cover plate includes a transparent material and a cushioning material. The encapsulating material covers the periphery of the image sensing chip, the periphery of the dam, part of the integrated circuit substrate and the periphery of the cover plate. The cushioning material is disposed between the transparent material and the dam and between the transparent material and the encapsulating material. The present invention reduces the possibility that the encapsulating material will peel off the cover plate.

Abstract: Disclosed is a method for manufacturing an image sensor module. The method comprises the steps of: disposing a glass cover on a substrate; sawing the glass cover into a plurality of glass units; forming an individual solidified interface filler between the adjacent glass units; sawing along the centerline of each solidified interface filler to form a plurality of independent electronic semi-finished products for complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS) packaging; and performing an image sensor molded ball grid array (ImBGA) process to obtain the image sensor module.

Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.

Abstract: A method for managing a memory apparatus including a plurality of physical blocks, and a volatile memory includes: obtaining a first host address and first data, and obtaining a second host address and second data; linking the first host address and second host address to a first page and second page of the physical block, and storing the first data and second data into the physical block; building a valid/invalid page count table according to a valid/invalid page count of the physical block; building a valid page position table according to the valid/invalid page count table, and storing the valid/invalid page count table in the volatile memory; and when a valid/invalid page count of the physical block indicates the physical block should be erased, using the valid page position table to move valid pages of the physical block to another physical block.

Abstract: A display device includes a casing, a display panel, and a camera module. The casing includes a bottom plate portion and a plurality of side plate portions, the plurality of side plate portions are respectively located at different sides of the bottom plate portion, and the of side plate portions and the bottom plate portion together define an accommodation space therebetween. The display panel is located in the accommodation space. One of the plurality of side plate portions has an inner side wall and a recess located at the inner side wall, the recess has an opening connected to the accommodation space and faces towards the display panel, and the camera module is accommodated in the recess.

Abstract: A method for managing a memory apparatus including a plurality of physical blocks, and a volatile memory includes: obtaining a first host address and first data, and obtaining a second host address and second data; linking the first host address and second host address to a first page and second page of the physical block, and storing the first data and second data into the physical block; building a valid/invalid page count table according to a valid/invalid page count of the physical block; building a valid page position table according to the valid/invalid page count table, and storing the valid/invalid page count table in the volatile memory; and when a valid/invalid page count of the physical block indicates the physical block should be erased, using the valid page position table to move valid pages of the physical block to another physical block.

Abstract: A method for managing a memory apparatus including a plurality of non-volatile (NV) memory elements includes: programming a physical block of a specific NV memory element, including: receiving a host command from a host; obtaining a host address and data from the host command; and linking the host address to a page of a physical block of the specific NV memory element and storing the data into the physical block. Before the pages of the physical block are fully programmed, a temporary local page linking address table is stored and is updated each time a linking relationship is changed. When the memory apparatus is to be shut down, the temporary local page linking address table is written to the specific NV memory element; and when the memory apparatus begins a start-up process, a global page address linking table is built by reading the local page address linking table.

Abstract: A method for preparing a fermented food by using a Rhizopus microsporus strain is provided. The method includes the following steps: providing an isolated and purified Rhizopus microsporus strain, and its deposit number is DSM 34400; and inoculating the isolated and purified Rhizopus microsporus strain to a substrate for fermentation to form a fermented food. The substrate includes a legume, a processing residue of a legume, or a combination thereof.

Abstract: A display device includes a casing, a display panel, and a camera module. The casing includes a bottom plate portion and a plurality of side plate portions, the plurality of side plate portions are respectively located at different sides of the bottom plate portion, and the of side plate portions and the bottom plate portion together define an accommodation space therebetween. The display panel is located in the accommodation space. One of the plurality of side plate portions has an inner side wall and a recess located at the inner side wall, the recess has an opening connected to the accommodation space and faces towards the display panel, and the camera module is accommodated in the recess.

Abstract: A method for managing a memory apparatus including a plurality of non-volatile (NV) memory elements includes: programming a physical block of a specific NV memory element, including: receiving a host command from a host; obtaining a host address and data from the host command; and linking the host address to a page of a physical block of the specific NV memory element and storing the data into the physical block. Before the pages of the physical block are fully programmed, a temporary local page linking address table is stored and is updated each time a linking relationship is changed. When the memory apparatus is to be shut down, the temporary local page linking address table is written to the specific NV memory element; and when the memory apparatus begins a start-up process, a global page address linking table is built by reading the local page address linking table.

Abstract: A method for managing a memory apparatus comprising a plurality of NV memory elements is disclosed. The method includes providing a physical block of each NV memory element with a local page address linking table by obtaining a first host address and first data from a first host command, and obtaining a second host address and second data from a second host command; linking the first host address to a first page of the physical block; and linking the second host address to a second page of the physical block. A global page address linking table is built by reading the local page address linking tables and stored in a volatile memory. For the local page address linking table, a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A method for managing a memory apparatus comprising a plurality of NV memory elements is disclosed. The method includes providing a physical block of each NV memory element with a local page address linking table by obtaining a first host address and first data from a first host command, and obtaining a second host address and second data from a second host command; linking the first host address to a first page of the physical block; and linking the second host address to a second page of the physical block. A global page address linking table is built by reading the local page address linking tables and stored in a volatile memory. For the local page address linking table, a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A memory apparatus includes: a plurality of non-volatile (NV) memory elements each including a plurality of physical blocks; a volatile memory for storing a global page address linking table; a transmission interface, for receiving commands from a host; and a processing unit, for obtaining a first host address and first data from a first host command, and a second host address and second data from a second host command, linking the first host address to a first page of a physical block and storing the first data in the first page, and linking the second host address to a second page of the physical block and storing the second data in the second page to build a local page address linking table; wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element including a plurality of physical blocks includes: obtaining a first host address and first data from a received first access command; obtaining a second host address and second data from a received second access command; linking the first host address to at least a first page of the physical block and linking the second host address to at least a second page of the physical block; storing the first data and second data into the physical block; and selectively erasing a portion of the physical block according to a valid/invalid page count of the physical block, the valid/invalid page count corresponding to accessing pages of the physical block. A difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A memory apparatus includes: a plurality of non-volatile (NV) memory elements each including a plurality of physical blocks; a volatile memory for storing a global page address linking table; a transmission interface, for receiving commands from a host; and a processing unit, for obtaining a first host address and first data from a first host command, and a second host address and second data from a second host command, linking the first host address to a first page of a physical block and storing the first data in the first page, and linking the second host address to a second page of the physical block and storing the second data in the second page to build a local page address linking table; wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element including a plurality of physical blocks includes: obtaining a first host address and first data from a received first access command; obtaining a second host address and second data from a received second access command; linking the first host address to at least a first page of the physical block and linking the second host address to at least a second page of the physical block; storing the first data and second data into the physical block; and selectively erasing a portion of the physical block according to a valid/invalid page count of the physical block, the valid/invalid page count corresponding to accessing pages of the physical block. A difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A memory apparatus includes at least one non-volatile memory element, which includes a plurality of physical blocks. A method for managing the memory apparatus includes: obtaining a first host address from a received first access command; linking the first host address to a first page of the physical block; obtaining a second host address from a received second access command; linking the second host address to a second page of the physical block; and selectively erasing a portion of the blocks according to a valid/invalid page count of the physical block corresponding to accessing pages of the physical block. A difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.