Abstract: A window ball grid array substrate and its package structure includes a package substrate with a long slot arranged thereon, wherein the improvement is characterized by the long slot penetrating an end of the package substrate making the package substrate appear to be U-shaped.

Abstract: A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections.

Abstract: A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections.

Abstract: A substrate panel is revealed, comprising a plurality of substrate strips where each substrate strip has a plurality of substrate units and a plurality of appropriative ID marks. Each ID mark is corresponding to and formed on each substrate unit. All of the ID marks are different in a manner to simultaneously recognize both the relative locations of the substrate units to the substrate strips and the relative locations of the substrate strips to the substrate panel. In a preferred embodiment, the ID marks are disposed on exposed surfaces of the substrate units so that it is still visible after semiconductor packaging. Therefore, during or after semiconductor packaging processes, any defect found can be traced back by the ID marks on the substrate units to recognize the locations of the substrate units in the substrate panel for failure analysis to improve PCB manufacturing processes or semiconductor packaging processes for better production yields.

Abstract: A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities.