Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending from over the first HVW region to over the second HVW region; a gate electrode on the gate dielectric; a drain region in the second HVW region; a source region at an opposite side of the gate dielectric than the drain region; and a deep well region of the first conductivity type underlying the second HVW region. Substantially no deep well region is formed directly underlying the drain region.

Abstract: An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region.

Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending from over the first HVW region to over the second HVW region; a gate electrode on the gate dielectric; a drain region in the second HVW region; a source region at an opposite side of the gate dielectric than the drain region; and a deep well region of the first conductivity type underlying the second HVW region. Substantially no deep well region is formed directly underlying the drain region.

Abstract: An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region.

Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.