Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

Abstract: A pulse-width-modulation (PWM) control system with nonlinear ramp is disclosed. A nonlinear ramp generator generates a nonlinear ramp varied with the duty (Vout/Vin) in a waveform signal, which could be a logarithm ramp, an exponent ramp, a multi-piecewise-linear ramp, a power ramp or a combination of above. The slope of the ramp is not a constant due to the non-linear characteristic. The voltage Vramp will vary with the input voltage Vin, output voltage Vout, and duty (Vout/Vin), therefore it will reduce the influence of the input voltage Vin or output voltage Vout on the modulation gain and loop gain, even to keep the modulation gain and loop gain in constant value. As mentioned-above, the present invention improves the transient response of system, the sensitivity for variation of Vin and Vout, thus it is capable of correcting the output voltage quickly, for supplying a more steady power output.

Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

Abstract: A pulse-width-modulation (PWM) control system with nonlinear ramp is disclosed. A nonlinear ramp generator generates a nonlinear ramp varied with the duty (Vout/Vin) in a waveform signal, which could be a logarithm ramp, an exponent ramp, a multi-piecewise-linear ramp, a power ramp or a combination of above. The slope of the ramp is not a constant due to the non-linear characteristic. The voltage Vramp will vary with the input voltage Vin, output voltage Vout, and duty (Vout/Vin), therefore it will reduce the influence of the input voltage Vin or output voltage Vout on the modulation gain and loop gain, even to keep the modulation gain and loop gain in constant value. As mentioned-above, the present invention improves the transient response of system, the sensitivity for variation of Vin and Vout, thus it is capable of correcting the output voltage quickly, for supplying a more steady power output.

Abstract: A method of fabricating a semiconductor memory device, particularly a mask ROM. A sacrificial oxide layer is formed on a silicon substrate and then a photoresist layer is formed on the sacrificial oxide layer. The photoresist layer is patterned to form a plurality of openings where bit lines are to extend respectively. Taking the patterned photoresist layer as a mask, arsenic ions are implanted into the silicon substrate through the openings and then boron ions are implanted into the silicon substrate through the openings. The implantation depth of boron ions are deeper than arsenic ions. The photoresist layer and the sacrificial oxide layer are removed after implantation. A gate oxide and a field oxide are grown simultaneously on the non-implanted and the implanted regions of the semiconductor layers respectively and a gate conductive layer is deposited on the silicon substrate.

Abstract: A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

Abstract: A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

Abstract: A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

Abstract: A method of fabricating a semiconductor memory device, particularly a mask ROM. A sacrificial oxide layer is formed on a silicon substrate and then a photoresist layer is formed on the sacrificial oxide layer. The photoresist layer is patterned to form a plurality of openings where bit lines are to extend respectively. Taking the patterned photoresist layer as a mask, arsenic ions are implanted into the silicon substrate through the openings and then boron ions are implanted into the silicon substrate through the openings. The implantation depth of boron ions are deeper than arsenic ions. The photoresist layer and the sacrificial oxide layer are removed after implantation. A gate oxide and a field oxide are grown simultaneously on the non-implanted and the implanted regions of the semiconductor layers respectively and a gate conductive layer is deposited on the silicon substrate.