Abstract: A frame correction method includes the following steps. Firstly, a correction frame is projected, wherein the correction frame has a number of original-boundary contour points. Then, in the first boundary contour adjustment, in response to a position adjustment of the first contour-adjusted one of the original-boundary contour points, correspondingly adjust the position of at least one symmetrical one of the original-boundary contour points, wherein at least one symmetrical one and the first contour-adjusted one are symmetrically disposed. Then, in response to the position adjustment of the first contour-adjusted one, a number of first new boundary contour points and a number of first open correction points are added.

Abstract: A frame correction method includes the following steps. Firstly, a correction frame is projected, wherein the correction frame has a number of original-boundary contour points. Then, in the first boundary contour adjustment, in response to a position adjustment of the first contour-adjusted one of the original-boundary contour points, correspondingly adjust the position of at least one symmetrical one of the original-boundary contour points, wherein at least one symmetrical one and the first contour-adjusted one are symmetrically disposed. Then, in response to the position adjustment of the first contour-adjusted one, a number of first new boundary contour points and a number of first open correction points are added.

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

Abstract: A projector includes an image converting module, a processing module and an imaging module. The image converting module receives an original image sequence with a first frame rate. The image converting module inserts a plurality of supplement images into the original image sequence per second to output a supplement image sequence with a second frame rate, wherein the second frame rate is larger than the first frame rate. The processing module is coupled to the image converting module. The processing module receives the supplement image sequence from the image converting module. The processing module ignores the supplement images and processes and outputs the original image sequence. The imaging module is coupled to the processing module. The imaging module receives the original image sequence from the processing module and outputs the original image sequence by the first frame rate.

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

Abstract: A projector includes an image converting module, a processing module and an imaging module. The image converting module receives an original image sequence with a first frame rate. The image converting module inserts a plurality of supplement images into the original image sequence per second to output a supplement image sequence with a second frame rate, wherein the second frame rate is larger than the first frame rate. The processing module is coupled to the image converting module. The processing module receives the supplement image sequence from the image converting module. The processing module ignores the supplement images and processes and outputs the original image sequence. The imaging module is coupled to the processing module. The imaging module receives the original image sequence from the processing module and outputs the original image sequence by the first frame rate.

Abstract: The disclosure provides an electronic device including a panel. The panel includes a display area, a first peripheral area and a plurality of driving units. The display area includes a plurality of odd-numbered gate lines and a plurality of even-numbered gate lines. The first peripheral area is disposed adjacent to the display area. The driving units are disposed in the first peripheral area and include a first driving unit group and a second driving unit group. The first driving unit group includes N driving units which correspond to N gate lines among first 2N of the odd-numbered gate lines or to N gate lines among first 2N of the even-numbered gate lines, wherein N is a positive integer greater than 1. The second driving unit group is disposed adjacent to the first driving unit group and includes 2P driving units which respectively correspond to P odd-numbered gate lines and P even-numbered gate lines.

Abstract: A touch display device at least including a gate driver is provided. The gate driver at least includes a pull-up control circuit, a pull-down control circuit and a pull-up output circuit. The pull-up control circuit sets the voltage level of a first node to a first voltage level. The pull-down control circuit is configured to set the voltage level of the first node to a second voltage level and includes a first transistor receiving an operation voltage. The second voltage level is lower than the first voltage level. The pull-up output circuit generates a scan signal according to the voltage level of the first node. During a first display period and a second display period, the operation voltage is equal to a first gate voltage. During a touch-sensing period, the operation voltage is equal to a second gate voltage that is lower than the first gate voltage.

Abstract: A display device including a panel having a gate driver is provided. The gate driver includes a multi-stage shift register. The N-th stage shift register includes a control module, a leakage compensation module, and an output module. The control module has a first terminal for receiving a first signal from the (N?M)-th stage shift register and a second terminal electrically connected to a node for transmitting a first signal to the node. The leakage compensation module has a third terminal electrically connected to the compensation voltage and a fourth terminal electrically connected to the node. The output module has a fifth terminal electrically connected to the node for receiving the first signal, and a sixth terminal for outputting a second signal of the N-th stage shift register for driving at least some parts of the pixel array. The compensation voltage charges the node during a touch sensing period.

Abstract: The invention provides a gate driving circuit for an in-cell touch panel to improve the issue wherein the undesired falling time of a pre-stage shift register and the undesired rising time of a next-stage shift register during a touch sensing period, in which the undesired falling time and the undesired rising time are caused by the output signal of the shift register cannot be correctly transmitted to the pre-stage shift register and the next-stage shift register during the touch sensing period.

Abstract: A display device including a panel having a gate driver is provided. The gate driver includes a multi-stage shift register. The N-th stage shift register includes a control module, a leakage compensation module, and an output module. The control module has a first terminal for receiving a first signal from the (N?M)-th stage shift register and a second terminal electrically connected to a node for transmitting a first signal to the node. The leakage compensation module has a third terminal electrically connected to the compensation voltage and a fourth terminal electrically connected to the node. The output module has a fifth terminal electrically connected to the node for receiving the first signal, and a sixth terminal for outputting a second signal of the N-th stage shift register for driving at least some parts of the pixel array. The compensation voltage charges the node during a touch sensing period.

Abstract: A gate driving circuit includes a plurality of shift registers arranged to output the gate driving signals in sequence. The shift registers are divided into groups arranged in sequence, wherein the driving signal from a first one of a N+1th group of shift registers is next to the driving signal from a first one of a Nth group of shift registers; and at least one first compensation circuit connected to the last one of the Nth group of shift registers and the first one of the N+1th group of shift registers, wherein the first compensation circuit provides a first control signal to enable the last one of the Nth group of shift registers to perform signal holding, and provides a second control signal to enable the first one of the N+1th group of shift registers to perform pre-charging, wherein N is an integer greater than zero.

Abstract: A touch display device at least including a gate driver is provided. The gate driver at least includes a pull-up control circuit, a pull-down control circuit and a pull-up output circuit. The pull-up control circuit sets the voltage level of a first node to a first voltage level. The pull-down control circuit is configured to set the voltage level of the first node to a second voltage level and includes a first transistor receiving an operation voltage. The second voltage level is lower than the first voltage level. The pull-up output circuit generates a scan signal according to the voltage level of the first node. During a first display period and a second display period, the operation voltage is equal to a first gate voltage. During a touch-sensing period, the operation voltage is equal to a second gate voltage that is lower than the first gate voltage.

Abstract: A test strip, a detecting device, and a detecting method are disclosed. The test strip includes a first specimen path, a first electrode set, a second specimen path, a second electrode set, and a reaction reagent. When the specimen contacts the first electrode set and the second electrode set, a first pulse signal and a second pulse signal are generated for obtaining a flow time of the specimen. When the specimen contacts the reaction reagent, the analyte concentration of the specimen can be obtained, and the concentration of the analyte can be corrected by the flow time.

Abstract: An anti-shake lens driving device includes a cover, a base, a movable part, a spring member, four upper magnets, four lower magnets, four driving coils and a circuit board. The cover has a through hole. The base is sleeved by the cover to form a central accommodation room. The movable part performs image-capturing through the through hole. The spring member is mounted exteriorly to the movable part to elastically fix the movable part inside the accommodation room. The upper magnets located above the spring member circle evenly the movable part. The lower magnets located below the spring member in a one-to-one matching manner with respect to the upper magnets circle evenly the movable part. The driving coils positioned individually corresponding to the upper/lower magnets circle evenly the movable part in a rectangle formation. The circuit board includes a circuit loop and electrically couples the driving coils.

Abstract: The invention provides a gate driving circuit for an in-cell touch panel to improve the issue wherein the undesired falling time of a pre-stage shift register and the undesired rising time of a next-stage shift register during a touch sensing period, in which the undesired falling time and the undesired rising time are caused by the output signal of the shift register cannot be correctly transmitted to the pre-stage shift register and the next-stage shift register during the touch sensing period.

Abstract: A gate driving circuit includes a plurality of shift registers connected in series. The shift registers include a plurality of output shift registers and X groups of dummy shift registers. The output shift registers output the gate driving signal to a plurality of gate driving lines of the pixel matrix in sequence. At least one of the X groups of dummy shift registers has J dummy shift registers and is connected between two adjacent output shift registers in the output shift registers, wherein at least one driving signal generated by the group of dummy shift registers is partially overlapped with the gate driving signal generated by the two adjacent output shift registers in a frame, wherein the X groups of dummy shift registers are not connected to the gate driving lines, and X and J are integers greater than zero.

Abstract: A gate driving circuit includes a plurality of shift registers arranged to output the gate driving signals in sequence. The shift registers are divided into groups arranged in sequence, wherein the driving signal from a first one of a N+1th group of shift registers is next to the driving signal from a first one of a Nth group of shift registers; and at least one first compensation circuit connected to the last one of the Nth group of shift registers and the first one of the N+1th group of shift registers, wherein the first compensation circuit provides a first control signal to enable the last one of the Nth group of shift registers to perform signal holding, and provides a second control signal to enable the first one of the N+1th group of shift registers to perform pre-charging, wherein N is an integer greater than zero.

Abstract: This disclosure provides a gate driver circuit in a display. The gate driver circuit includes shift registers configured for receiving clock and start signals and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a panel, each register comprising: a control unit having a clock input, a first voltage input, a second voltage input, and a first output; and a first output unit having a first pull-down TFT electrically connected to one of the first outputs and a gate-driving terminal configured for providing the gate signal; wherein one of the clock signals at the clock input is provided to the first output unit; and a first control signal's period at the first output is longer than the clock signal's period at the clock input and shorter than the period of a frame.