Abstract: A position-encoding device includes a sensing device, a filtering device, a calibrating device and a compensating device. The sensing device senses the motion of a moving device to generate first and second signals. The filtering device filters the first and second signals to generate first and second filtering signal. The calibrating device captures the first and second filtering signals to obtain time and phase information of the first and second filtering signals, performs gain and offset calibration on the first and second filtering signals, and performs a phase calibration on the first and second filtering signals through first, second feedback signals and the time and phase information of the first and second filtering signals to generate first and second calibrating signals. The compensating device compensates for the first and second calibrating signals according to a lookup table, so as to generate first and second position encoding signals.

Abstract: A method for controlling a resistive random access memory (ReRAM) is proposed. The method calculates a number of a bit value of a data when the data is to be written to the resistive random access memory. Each bit of the data is flipped and the data is written to the ReRAM if the number of the bit value is greater than a half of a length of the data. The data as it original is written to the ReRAM if the number of the bit value is less than a half of the length of the data.

Abstract: A position-encoding device includes a sensing device, a filtering device, a calibrating device and a compensating device. The sensing device senses the motion of a moving device to generate first and second signals. The filtering device filters the first and second signals to generate first and second filtering signal. The calibrating device captures the first and second filtering signals to obtain time and phase information of the first and second filtering signals, performs gain and offset calibration on the first and second filtering signals, and performs a phase calibration on the first and second filtering signals through first, second feedback signals and the time and phase information of the first and second filtering signals to generate first and second calibrating signals. The compensating device compensates for the first and second calibrating signals according to a lookup table, so as to generate first and second position encoding signals.

Abstract: A data transfer system is provided. The system includes a plurality of electronic devices and a data transfer management device. The data transfer management device identifies a master device among the electronic devices, and the data transfer device make the master device as a root node of a topology architecture, wherein the master device is configured to provide data. The data transfer device calculates a maximum connection amount according to a first transfer time, wherein the data transfer device selects a plurality of slave devices among the electronic devices according to the maximum connection amount. The data transfer device divides the master device into a transmitting node queue, and arranges the slave devices into a receiving node queue in sequence. And, the data transfer device builds a plurality of layers of the topology architecture and sets a plurality of layer transfers corresponding to the layers.

Abstract: A wideband transimpedance amplifier circuit is provided. The wideband transimpedance amplifier circuit includes a common-gate transistor, a bias current controlling circuit and an amplifier circuit. The bias current controlling circuit is coupled to a source of the common-gate transistor. The amplifier circuit is coupled to a drain of the common-gate transistor. The bias current controlling circuit adjusts the input impedance of the wideband transimpedance amplifier circuit according to the output signal of the amplifier circuit.

Abstract: A wideband transimpedance amplifier circuit is provided. The wideband transimpedance amplifier circuit includes a common-gate transistor, a bias current controlling circuit and an amplifier circuit. The bias current controlling circuit is coupled to a source of the common-gate transistor. The amplifier circuit is coupled to a drain of the common-gate transistor. The bias current controlling circuit adjusts the input impedance of the wideband transimpedance amplifier circuit according to the output signal of the amplifier circuit.

Abstract: A method for controlling a resistive random access memory (ReRAM) is proposed. The method calculates a number of a bit value of a data when the data is to be written to the resistive random access memory. Each bit of the data is flipped and the data is written to the ReRAM if the number of the bit value is greater than a half of a length of the data. The data as it original is written to the ReRAM if the number of the bit value is less than a half of the length of the data.

Abstract: An energy-efficient nonvolatile microprocessor includes a processing core, a nonvolatile flip-flop array, a set of nonvolatile interconnections, and a store-enable register. When a power source is recovered to a stable state, the processing core determines whether data of nonvolatile registers is not transmitted before power-off. If yes, the processing core executes programmable recovery entry decision to avoid recovery failures for different applications. The processing core has plural system states divided into programmer visible states and programmer invisible states. The nonvolatile interconnections are connected between the processing core and the nonvolatile flip-flop array. When the power source is unstable, the processing core only stores the programmer visible states into the nonvolatile flip-flop array and, at the same time, only stores the system states of the peripheral modules corresponding to the bits of the store-enable register that are set to be “true” into the nonvolatile flip-flop array.

Abstract: A data transfer system is provided. The system includes a plurality of electronic devices and a data transfer management device. The data transfer management device identifies a master device among the electronic devices, and the data transfer device make the master device as a root node of a topology architecture, wherein the master device is configured to provide data. The data transfer device calculates a maximum connection amount according to a first transfer time, wherein the data transfer device selects a plurality of slave devices among the electronic devices according to the maximum connection amount. The data transfer device divides the master device into a transmitting node queue, and arranges the slave devices into a receiving node queue in sequence. And, the data transfer device builds a plurality of layers of the topology architecture and sets a plurality of layer transfers corresponding to the layers.

Abstract: A non-volatile static random access memory has an operating mode, a data backup mode and a data restore mode. The non-volatile static random access memory includes a memory cell and a power saving module. The memory cell includes a latch, a set of latch switch units, a set of backup memory units, a set of backup activation units, a backup setting unit and a driving signal transmission unit. The power saving module includes a control switch unit, a backup determination unit and a restore switch unit. When backup data is different from data stored in the latch, a backup driving signal is generated by a node voltage of the backup memory units and outputted to a backup determination unit, which drives the backup setting unit to turn on according to the backup driving signal, so as to change the backup data in the backup memory units and ensure correct backup.

Abstract: A lighting apparatus of adjustable color temperature including a luminescent source, a controller and a detector is proposed. The luminescent source is configured to provide an illumination source. The controller is coupled to the luminescent source. The controller is configured to adjust a color temperature of the illumination source according to at least one of global and local color temperatures. The detector is coupled to the controller. The detector is configured to detect a color temperature of a location of the lighting apparatus of adjustable color temperature, so as to provide the local color temperature to the controller. The controller performs a weighting operation for the global and local color temperatures to obtain an operation result for adjusting the color temperature of the illumination source. A method for adjusting color temperature of a lighting apparatus of adjustable color temperature is also proposed.

Abstract: A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided.

Abstract: A lighting apparatus of adjustable color temperature including a luminescent source, a controller and a detector is proposed. The luminescent source is configured to provide an illumination source. The controller is coupled to the luminescent source. The controller is configured to adjust a color temperature of the illumination source according to at least one of global and local color temperatures. The detector is coupled to the controller. The detector is configured to detect a color temperature of a location of the lighting apparatus of adjustable color temperature, so as to provide the local color temperature to the controller. The controller performs a weighting operation for the global and local color temperatures to obtain an operation result for adjusting the color temperature of the illumination source. A method for adjusting color temperature of a lighting apparatus of adjustable color temperature is also proposed.

Abstract: An energy-efficient nonvolatile microprocessor includes a processing core, a nonvolatile flip-flop array, a set of nonvolatile interconnections, and a store-enable register. When a power source is recovered to a stable state, the processing core determines whether data of nonvolatile registers is not transmitted before power-off. If yes, the processing core executes programmable recovery entry decision to avoid recovery failures for different applications. The processing core has plural system states divided into programmer visible states and programmer invisible states. The nonvolatile interconnections are connected between the processing core and the nonvolatile flip-flop array. When the power source is unstable, the processing core only stores the programmer visible states into the nonvolatile flip-flop array and, at the same time, only stores the system states of the peripheral modules corresponding to the bits of the store-enable register that are set to be “true” into the nonvolatile flip-flop array.

Abstract: A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided.

Abstract: A non-volatile static random access memory has an operating mode, a data backup mode and a data restore mode. The non-volatile static random access memory includes a memory cell and a power saving module. The memory cell includes a latch, a set of latch switch units, a set of backup memory units, a set of backup activation units, a backup setting unit and a driving signal transmission unit. The power saving module includes a control switch unit, a backup determination unit and a restore switch unit. When backup data is different from data stored in the latch, a backup driving signal is generated by a node voltage of the backup memory units and outputted to a backup determination unit, which drives the backup setting unit to turn on according to the backup driving signal, so as to change the backup data in the backup memory units and ensure correct backup.

Abstract: A resistive random access memory (ReRAM) and a method for controlling the ReRAM are proposed. The method detects a temperature of the ReRAM and set a reference resistance of a sense amplifier of the ReRAM according to the temperature. In addition, the method adapts to temperature fluctuation by switching operating mode based on the temperature of the ReRAM to enhance the reliability of the ReRAM. The control method may include a self-adaptive write mechanism, which takes write errors and data retention errors under high temperature into consideration at the same time. The control method may include a self-adaptive error correcting code mechanism, which determines the number of write errors according to Write-and-Verify (WAV) of writing and chooses the ECC algorithm. The control method may include a programmable WAV mechanism, programmably dividing N steps of WAV into two parts, so as to facilitate a memory write speed.