Patents by Inventor Tsai-Ko Teng

Tsai-Ko Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9437311
    Abstract: A flash memory apparatus and an initialization method for programming operation thereof are provided. The initialization method includes: providing a plurality of increasing programming pulse voltages to operate a plurality of without program inhibit programming actions on memory cells of the flash memory, and operating a plurality of programming verification actions on the memory cells according to a programming verification voltage; obtaining a recorded programming voltage value according verified results of the programming verification actions; providing a plurality of increasing reading pulse voltages to operate a plurality of reading actions on the memory cells; obtaining a recorded reading voltage value according to read result of the reading actions; and obtaining an initial programming voltage and an incremental step programming pulse voltages according to the recorded programming voltage value, the recorded reading voltage value and a voltage value of the programming verification voltage.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 6, 2016
    Assignee: Powerchip Technology Corporation
    Inventor: Tsai-Ko Teng
  • Patent number: 9384844
    Abstract: A flash memory apparatus and data erasing method thereof. The data erasing method includes: setting a plurality of incremental erasing voltages sequentially, and operating a plurality of data erasing operations on memory cells according to the erasing voltages; recording a recoded erasing voltage corresponding to the last data erasing operation; setting a plurality of incremental reading voltage sequentially, operating a plurality of data reading operations on the memory cells, and recording a final reading voltage corresponding to the last reading operation; setting a final erasing voltage for operating a final erasing operation on the memory cells, wherein a voltage level of the final erasing voltage equals to a sum of voltage levels of an erasing verification voltage, the final reading voltage and the recorded erasing voltage.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: July 5, 2016
    Assignee: Powerchip Technology Corporation
    Inventor: Tsai-Ko Teng