Abstract: A digital signal processor includes an instruction analysis unit, a digital signal processor (DSP) core and a memory unit. The instruction analysis unit receives an instruction and determines the required bit width M for the data process corresponding to the instruction. The DSP core performs the M-bit data process based on the bit width M determined by the instruction analysis unit, and the memory unit stores multiple data and performs the M-bit access based on the bit width M determined by the instruction analysis unit thereby allowing the DSP core to access, and at least one available space in the memory unit will be adjusted such that only the access space having the bit width M for the operation corresponding to the instruction will be open in each access, thereby effectively achieving the effect of power-saving.

Abstract: A method for optimizing energy consumption of an application program for a DSP includes a program code generating unit is adapted to edit and generate a program code, a program compiling unit is adapted to receive the program code, and according to the program code and the instructional wise energy consumption database generate a plurality of assembly codes, and a DSP simulator adapted to receive the assembly codes and at least one stimulus to simulate the total and the amount of energy every instruction of the assembly codes consumes and transmit the results to the program compiling unit. The program compiling unit modifies the compiling scheme to recompile the program code and transmits the new assembly codes to the DSP simulator, until the simulation results reach or are lower than a predetermined energy consumption value.

Abstract: A developing system and method for optimizing the energy consumption of an application program for a DSP are provided.

Abstract: A digital signal processor comprises an instruction analysis unit, a digital signal processor (DSP) core and a memory unit. The instruction analysis unit receives an instruction and determines the required bit width M for the data process corresponding to the instruction. The DSP core performs the M-bit data process based on the bit width M determined by the instruction analysis unit, and the memory unit stores multiple data and performs the M-bit access based on the bit width M determined by the instruction analysis unit thereby allowing the DSP core to access, and at lest one available space in the memory unit will be adjusted such that only the access space having the bit width M for the operation corresponding to the instruction will be open in each access, thereby effectively achieving the effect of power-saving.