Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract: A switched capacitance circuit selectively provides a capacitance across first and second output nodes in response to a selection control signal. The switched capacitance circuit may include a first capacitor coupled between the first output node and a mid-node, a second capacitor coupled between the second output node and the mid-node, and a switching circuit. The switching circuit is configured to switch the first and second capacitors in response to the selection control signal and to provide a bias voltage at the mid-node in response to the selection control signal.

Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.

Abstract: A switched capacitance circuit selectively provides a capacitance across first and second output nodes in response to a selection control signal. The switched capacitance circuit may include a first capacitor coupled between the first output node and a mid-node, a second capacitor coupled between the second output node and the mid-node, and a switching circuit. The switching circuit is configured to switch the first and second capacitors in response to the selection control signal and to provide a bias voltage at the mid-node in response to the selection control signal.

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

Abstract: Metal-oxide-metal (MOM) type capacitors include a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric layer; a first set of fingers formed on the first dielectric layer, the first set of fingers being coupled to the first terminal via a conductive trace formed on a second dielectric layer; a second terminal configured to receive second voltage, the second terminal being formed on the first dielectric layer; and a second set of fingers formed on the first dielectric layer, the second set of fingers being coupled to the second terminal, wherein the fingers of the second set are interspersed with the fingers of the first set.

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

Abstract: Metal-oxide-metal (MOM) type capacitors include a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric layer; a first set of fingers formed on the first dielectric layer, the first set of fingers being coupled to the first terminal via a conductive trace formed on a second dielectric layer; a second terminal configured to receive second voltage, the second terminal being formed on the first dielectric layer; and a second set of fingers formed on the first dielectric layer, the second set of fingers being coupled to the second terminal, wherein the fingers of the second set are interspersed with the fingers of the first set.

Abstract: An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.

Abstract: An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.

Abstract: Aspects of a reconfigurable varactor array for providing a capacitance to control an output frequency of a voltage-controlled oscillator are provided. The reconfigurable varactor array can be configured to provide a configurable capacitance. The reconfigurable varactor array can include a plurality of varactor cells connected in parallel. The reconfigurable varactor array can also include a control circuit configured to receive a control signal to select the configurable capacitance from the reconfigurable varactor array. The control circuit can include a plurality of switch groups. Each switch group can be separately connected to one varactor cell in the reconfigurable varactor array. The control signal from the control circuit can control operation of each switch group.

Abstract: An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.