Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. A method of forming a gate oxide on a substrate comprises providing a substrate having thereon a plurality of trenches having gate oxides formed therein, wherein the plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer disposed thereon and used to form the plurality of trenches. The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions.

Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.

Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.

Abstract: The present invention provides a method for fabricating semiconductor devices, which includes the following steps. First, a silicide layer is formed on a substrate. Then, the silicide layer is defined, and an oxide layer is formed uniformly on the substrate and the silicide layer. Next, the oxide layer is etched to form a sidewall oxide layer by dry etching process, and the remaining oxide layer on the substrate is removed by wet etching. Next, inactive gas is added to the surface of the silicide layer to perform an anneal process. Finally, a mask oxide layer is formed on the silicide layer.

Abstract: The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract: A method of contact ion implantation is disclosed. Only one mask and a dosage-enhanced implantation is utilized to form different types of doped contact regions. A blanket ion implantation is first carried out, and all the contact regions of first and second type are formed with the first conductive type impurities. Then a mask is defined to cover the first type contact regions and expose the second type regions. A second ion implantation is now carried out to implant impurity ions of second conductive type into the second type contact regions. The dosage of these second conductive type ions is determined so that, the second type contact regions are convert from the first conductive type into section conductive type.