Patents by Inventor Tsai-Sheng Chiu

Tsai-Sheng Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111210
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: May 9, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20240112912
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: July 28, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20050138225
    Abstract: A universal serial bus integrated device. The integrated device comprises a housing and an integrated circuit board. The integrated circuit board is disposed in the housing, comprising a plurality of universal serial bus slots thereon.
    Type: Application
    Filed: March 17, 2004
    Publication date: June 23, 2005
    Inventor: Tsai-Sheng Chiu
  • Patent number: 6906929
    Abstract: A computer backplane is disposed with at least an AGP slot, a PCI slot and/or an EISA slot. The PCI slot can be used to electrically connect with PCI cards. The EISA slot and the PCI slot are in alignment to allow that a CPU card can be connected simultaneously to both the EISA slot and the PCI slot. The AGP slot is used to electrically connect with an AGP card. Such an arrangement allows for ease of replacement of the AGP card and a lower production cost.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 14, 2005
    Assignee: ICP Electronics Inc.
    Inventor: Tsai-Sheng Chiu
  • Publication number: 20040064628
    Abstract: An improved backplane with an accelerated graphic port (AGP) in industrial computer for electrically connecting a CPU interface card therein. The backplane has at least a first type bus expansion slot, a second type bus expansion slot, a bus bridge device, and an AGP slot mounted thereon. The bus bridge device is designed as converting different-type bus signals between the first type bus expansion slot and the second type bus expansion slot when the first type bus expansion slot receives the CPU interface card therein. By way of the design of mounting the AGP slot and the bus bridge device on the backplane, the volume of CPU interface card can be reduced and therefore does not occupy the demanded space of other adjacent interface cards, and converts a variety of signals from the backplane.
    Type: Application
    Filed: April 10, 2003
    Publication date: April 1, 2004
    Inventor: Tsai-Sheng Chiu
  • Publication number: 20040024940
    Abstract: A central processing unit (CPU) card with an accelerated graphic port (AGP) is disclosed herein. The CPU card is formed with PCI contact pads and AGP contact pads, or/and EISA contact pads. The PCI contact pads, and/or EISA contact pads and AGP contact pads are respectively inserted into a PCI expansion slot and an EISA expansion slot or an AGP expansion slot. As the result, transmission of image and data signals are implemented between the CPU card and a computer backplane by way of insertion of the AGP and/or EISA contact pads, in the AGP bus. Therefore, the present invention is capable of improving conventional technology in need of usage of flat cables to electrically interconnect between a required external AGP card and the CPU card, and in a lower running speed.
    Type: Application
    Filed: September 27, 2002
    Publication date: February 5, 2004
    Inventor: Tsai-Sheng Chiu
  • Publication number: 20030123219
    Abstract: A computer backplane is disposed with at least an AGP slot, a PCI slot and/or an EISA slot. The PCI slot can be used to electrically connect with PCI cards. The EISA slot and the PCI slot are in alignment to allow that a CPU card can be connected simultaneously to both the EISA slot and the PCI slot. The AGP slot is used to electrically connect with an AGP card. Such an arrangement allows for ease of replacement of the AGP card and a lower production cost.
    Type: Application
    Filed: September 27, 2002
    Publication date: July 3, 2003
    Inventor: Tsai-Sheng Chiu