Abstract: An integrated transmission circuit and method for transmitting output data to a chipset via a transmission interface are provided. The integrated transmission circuit includes a first application circuit, a second application circuit, a media access control (MAC) circuit, and a physical layer (PHY) circuit. The first application circuit is used for receiving and processing first data to output first processed data. The second application circuit is used for receiving and processing second data to output second processed data. The MAC circuit is coupled to the first application circuit and the second application circuit, and used for encoding the first processed data and the second processed data so as to output encoded data. The PHY circuit is coupled to the MAC circuit to receive the encoded data so as to output the output data to the transmission interface.

Abstract: An integrated transmission circuit and method for transmitting output data to a chipset via a transmission interface are provided. The integrated transmission circuit includes a first application circuit, a second application circuit, a media access control (MAC) circuit, and a physical layer (PHY) circuit. The first application circuit is used for receiving and processing first data to output first processed data. The second application circuit is used for receiving and processing second data to output second processed data. The MAC circuit is coupled to the first application circuit and the second application circuit, and used for encoding the first processed data and the second processed data so as to output encoded data. The PHY circuit is coupled to the MAC circuit to receive the encoded data so as to output the output data to the transmission interface.

Abstract: The invention provides a device by using a pipelined architecture for enhancing the efficiency and speed of encryption/authentication. To handle all modes defined in RFC2401, 3 DES-HMAC sub-engines are built in the IPSEC engine. Each DES-HMAC sub-engine includes one DES engine and one HMAC engine. By utilizing the pipelined architecture for the combinations of multiple modes, it does not take any waiting time in the encryption and authentication processing. A data block is immediately sent to the next DES_HMAC sub-engine for the next encryption and authentication process right after the previous DES_HMAC sub-engine has outputted the data block.