Abstract: A method and system for encoding a digital video signal using a plurality of parallel processors. A digital picture is received that is composed of one or more GOPs. The CPU then determines the number of GOPs that need to be encoded and divides them into groups. The number of GOPs in a group may equal the number of parallel processors in the multi-core platform available to encode. The CPU transfers in a single batch to the multi-core platform, a frame of equal rank from each GOP contained in the first group. The multi-core platform encodes the frames in parallel, rearranges the encoded byte stream chunk into normal display order sequence and stores the encoded byte stream. The process may repeat until all the GOPs in the first group have been encoded. Upon completion the multi-core platform outputs the encoded byte stream in normal display order sequence.

Abstract: A method and system for encoding a digital video signal using a plurality of parallel processors. A digital picture is received that is composed of one or more GOPs. The CPU then determines the number of GOPs that need to be encoded and divides them into groups. The number of GOPs in a group may equal the number of parallel processors in the multi-core platform available to encode. The CPU transfers in a single batch to the multi-core platform, a frame of equal rank from each GOP contained in the first group. The multi-core platform encodes the frames in parallel, rearranges the encoded byte stream chunk into normal display order sequence and stores the encoded byte stream. The process may repeat until all the GOPs in the first group have been encoded. Upon completion the multi-core platform outputs the encoded byte stream in normal display order sequence.

Abstract: Systems and methods consistent with the invention relate to performing faster motion estimation through efficient use of the General Purpose Graphic Processing Unit (GPGPU) as the compute co-processor in a multi-processor architecture. Integer pel motion estimation and fractional pel motion estimation algorithms for large block sizes may be performed on the GPU, while motion estimation for smaller block sizes is performed on the central processing unit (CPU). In embodiments described herein, GPU-based integer pel motion estimation and fractional pel motion estimation algorithms are performed using kernels which are designed so that multiple thread blocks can run concurrently on a multiprocessor.

Abstract: A method of and an apparatus for parallel processing video compression is described herein. A picture is divided into N zones vertically, and Vertical Split Parallelism (VSP) deploys N+1 processes: N M-coding processes for general macroblock coding in N zones and one E-coding process for entropy coding. By dividing a macroblock encoding process into M-coding and E-coding processes, multiple M-coding threads and one E-coding thread are able to progress simultaneously with proper synchronization between threads. Since the workload of M-coding processes is greater than E-coding for each macroblock coding process, two cores are able to be designated to the two M-coding processes. Either of the cores are able to be designated to the E-coding process since the workload of E-coding is light. Therefore, VSP utilizes parallel processing computing power efficiently.

Abstract: A method of and an apparatus for parallel processing video compression is described herein. A picture is divided into N zones vertically, and Vertical Split Parallelism (VSP) deploys N+1 processes: N M-coding processes for general macroblock coding in N zones and one E-coding process for entropy coding. By dividing a macroblock encoding process into M-coding and E-coding processes, multiple M-coding threads and one E-coding thread are able to progress simultaneously with proper synchronization between threads. Since the workload of M-coding processes is greater than E-coding for each macroblock coding process, two cores are able to be designated to the two M-coding processes. Either of the cores are able to be designated to the E-coding process since the workload of E-coding is light. Therefore, VSP utilizes parallel processing computing power efficiently.