Abstract: A multiple-microcontroller integrated circuit chip comprises at least two microcontrollers capable of operating independently, a plurality of pins, a data bus, a pin multiple-control register, and a plurality of pin control logics. The pin multiple-control register, the data bus, and the pin control logics are electrically connected to the pins. The microcontrollers can be functionally connected to at least one predetermined pin so that the microcontrollers may read the setting status of the pin to check whether the pin is available, and to set the functional mode or the attributes, of the pin. The multiple-microcontroller integrated circuit chip can therefore provide more functions and higher flexibility with the least number of pins.

Abstract: A single chip multiple-microcontroller package structure comprises at least two microcontrollers capable of operating independently, a plurality of pins, a data bus, a pin multiple-control register, and a plurality of pin control logics. The pin multiple-control register, the data bus, and the pin control logics are electrically connected to the pins. The microcontrollers can be electrically connected to at least a specific pin in the pins at the same time so that the specific pin can be dynamically controlled by the microcontrollers for data access and function change of the specific pin. The single chip multiple-microcontroller package structure can therefore provide more functions and higher flexibility with the least pins.

Abstract: A single-chip multiple-microcontroller architecture and a timing control method for the same are proposed. The single-chip multiple-microcontroller architecture comprises multiple microcontrollers integrated into a single chip. Different microcontrollers are separately executed at mutually exclusive timings, equivalent to several microcontrollers that operate parallel and independently. Therefore, multiple microcontrollers can be realized in a single IC chip to accomplish the effect of parallel processing.

Abstract: A computer architecture that incorporates display memory into system memory is disclosed, which comprises a memory, a memory controller and a display controller. Both of the memory controller and the display controller are employed to control access of the memory device having system data and display data stored therein. Built-in signals and an arbiter are provided between the controllers to arbitrate the priorities of the two controllers to access the memory device. Furthermore, request and grant signals are used to initiate the refresh of the main memory to maintain data therein. The control circuits of the two controllers to the memory device are connected to each other to prevent signals contention.