Patents by Inventor Tsan-Chi Chu
Tsan-Chi Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8536653Abstract: A metal oxide semiconductor transistor includes a substrate including a first well, a second well, and an insulation between the first well and the second well, a first gate structure disposed on the first well, a second gate structure disposed on the second well, four first dopant regions disposed in the substrate at two sides of the first gate structure, and in the substrate at two sides of the second gate structure respectively, two second dopant regions disposed in the substrate at two sides of the first gate structure respectively, two first epitaxial layers disposed in the substrate at two sides of the first gate structure respectively and two first source/drain regions disposed in the substrate at two sides of the first gate structure respectively, wherein each of the first source/drain regions overlaps with one of the first epitaxial layers and one of the second dopant regions simultaneously.Type: GrantFiled: October 14, 2010Date of Patent: September 17, 2013Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Patent number: 8409945Abstract: A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate beside the gate.Type: GrantFiled: January 5, 2011Date of Patent: April 2, 2013Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Patent number: 8022503Abstract: An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.Type: GrantFiled: June 3, 2008Date of Patent: September 20, 2011Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Wen-Shiang Liao, Tsan-Chi Chu
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Patent number: 7998821Abstract: A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.Type: GrantFiled: October 5, 2006Date of Patent: August 16, 2011Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20110097866Abstract: A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate besdie the gate.Type: ApplicationFiled: January 5, 2011Publication date: April 28, 2011Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Patent number: 7902587Abstract: A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectric layer, and two doped regions in the substrate beside the gate.Type: GrantFiled: April 17, 2008Date of Patent: March 8, 2011Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20110031555Abstract: A metal oxide semiconductor transistor includes a substrate including a first well, a second well, and an insulation between the first well and the second well, a first gate structure disposed on the first well, a second gate structure disposed on the second well, four first dopant regions disposed in the substrate at two sides of the first gate structure, and in the substrate at two sides of the second gate structure respectively, two second dopant regions disposed in the substrate at two sides of the first gate structure respectively, two first epitaxial layers disposed in the substrate at two sides of the first gate structure respectively and two first source/drain regions disposed in the substrate at two sides of the first gate structure respectively, wherein each of the first source/drain regions overlaps with one of the first epitaxial layers and one of the second dopant regions simultaneously.Type: ApplicationFiled: October 14, 2010Publication date: February 10, 2011Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Patent number: 7732886Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.Type: GrantFiled: July 15, 2008Date of Patent: June 8, 2010Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu, Wen-Shiang Liao, Wen-Ching Tsai
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Publication number: 20100012974Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.Type: ApplicationFiled: July 15, 2008Publication date: January 21, 2010Inventors: Hung-Lin Shih, Tsan-Chi Chu, Wen-Shiang Liao, Wen-Ching Tsai
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Publication number: 20090294903Abstract: An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hung-Lin Shih, Wen-Shiang Liao, Tsan-Chi Chu
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Publication number: 20090261401Abstract: A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectirc layer, and two doped regions in the substrate beside the gate.Type: ApplicationFiled: April 17, 2008Publication date: October 22, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20080085577Abstract: A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.Type: ApplicationFiled: October 5, 2006Publication date: April 10, 2008Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Patent number: 6569253Abstract: The present invention provides a method of cleaning a chamber of a CVD machine and elements within. A gas mixture of carbon tetrafluoride (CF4) and perfluoro ethane (C2F6) is first injected into the chamber. After performing a surface treatment, comprising a sandblasting step or a polishing step, on the surfaces of the elements, the elements are then immersed in a cleaning solution, comprising at least ammonia water (NH4OH) and hydrogen peroxide (H2O2) at a temperature maintained between 40° C. to 70° C. Finally, the temperature of the cleaning solution is raised so that the residual layer on the surface of the elements can drop from the surfaces of the heater and the process kits or dissolve into the cleaning solution.Type: GrantFiled: April 25, 2001Date of Patent: May 27, 2003Assignee: United Microelectronics Corp.Inventors: Wei-Hsu Wang, Tsan-Chi Chu, Cheng-Yuan Yao, Wei-Hao Lee, Ping-Chung Chung
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Publication number: 20020157687Abstract: The present invention provides a method of cleaning a chamber of a CVD machine and elements within. A gas mixture of carbon tetrafluoride (CF4) and perfluoro ethane (C2F6) is first injected into the chamber. After performing a surface treatment, comprising a sandblasting step or a polishing step, on the surfaces of the elements, the elements are then immersed in a cleaning solution, comprising at least ammonia water (NH4OH) and hydrogen peroxide (H2O2) at a temperature maintained between 40° C. to 70° C. Finally, the temperature of the cleaning solution is raised so that the residual layer on the surface of the elements can drop from the surfaces of the heater and the process kits or dissolve into the cleaning solution.Type: ApplicationFiled: April 25, 2001Publication date: October 31, 2002Inventors: Wei-Hsu Wang, Tsan-Chi Chu, Cheng-Yuan Yao, Wei-Hao Lee, Ping-Chung Chung