Patents by Inventor Tsan-Hua Tung

Tsan-Hua Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964594
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Publication number: 20190122929
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Patent number: 10163711
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Publication number: 20170271209
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Patent number: 9673098
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Publication number: 20160343615
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Patent number: 9406581
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Patent number: 9312148
    Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: April 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
  • Publication number: 20150364395
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Patent number: 9117682
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 25, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Publication number: 20150187605
    Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 2, 2015
    Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG
  • Patent number: 9000584
    Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
  • Publication number: 20130168848
    Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG
  • Publication number: 20130087916
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 11, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Publication number: 20120153520
    Abstract: The invention discloses the synthesis of a new-type chitosan-based hybrid macromolecule and a method for producing or using the macromolecule. This macromolecule comprises an amphiphatic chitosan and a silicon-based coupling agent that is anchored by a chemical bonding. The method for producing the hybrid macromolecule can be easily operated under ambient environment. The produced macromolecule can be self-assembled in an aqueous environment to form a nanocarrier, and has the ability to efficiently encapsulate drugs for a subsequent sustained release purpose. This self-assembled hybrid nanocarrier demonstrated features of excellent biocompatibility, drug loading ability and cellular uptake efficiency.
    Type: Application
    Filed: May 5, 2011
    Publication date: June 21, 2012
    Inventors: Dean-Mo LIU, Tsan-Hua Tung, Hongwei Cheng