Abstract: A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports.

Abstract: A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports.

Abstract: A touch display apparatus is disclosed. Without additional touch device, either the reversed AM structure or a conventional PM structure is provided to combine with the human body's conductive properties and the noise-immune sensing circuit design, thereby to achieve the purpose of displaying images and performing multi-touch detection simultaneously. Thus, the hardware cost and the power consumption are reduced.

Abstract: A ghost cancellation method for the multi-touch sensitive device is disclosed. The multi-touch sensitive device includes a sensing array having multiple lines of a first axis and multiple lines of a second axis intersecting with each other. All the lines of the sensing array are scanned to determine which ones of the lines are touched, so as to determine touch point candidates. For each touch point candidate, a driving signal is applied to the line of the first axis, and the line of the second axis is detected to check if the touch point candidate is actually touched.

Abstract: A ghost cancellation method for the multi-touch sensitive device is disclosed. The multi-touch sensitive device includes a sensing array having multiple lines of a first axis and multiple lines of a second axis intersecting with each other. All the lines of the sensing array are scanned to determine which ones of the lines are touched, so as to determine touch point candidates. For each touch point candidate, a driving signal is applied to the line of the first axis, and the line of the second axis is detected to check if the touch point candidate is actually touched.

Abstract: A touch display apparatus is disclosed. Without additional touch device, either the reversed AM structure or a conventional PM structure is provided to combine with the human body's conductive properties and the noise-immune sensing circuit design, thereby to achieve the purpose of displaying images and performing multi-touch detection simultaneously. Thus, the hardware cost and the power consumption are reduced.

Abstract: The present invention discloses a speed adjustment system and method for performing the same, which is capable to provide different power saving behaviors adaptive for different applications (e.g. a mobile or a normal configuration) and/or different-corner-process chips. The speed adjustment system includes a reference speed generator for pre-storing multiple reference speed value, an operating speed generator for pre-storing multiple operating speed value, a comparing unit for determining whether a predefined logical operational relationship is satisfied with the operating speed value and reference speed value, a voltage controller based on said determination result to vary the operating voltage, and a speed detector for detecting the operating speed value.

Abstract: The present invention discloses a request transmission mechanism and a method thereof capable of reducing request transmission time. The method and mechanism in accordance with the present invention allow a request to bypass unnecessary stages in a computer system by usage of a bypassing rule and a dependence controller. The dependence controller comprises a comparator capable of receiving the instruction from the dependence controller and enabling a designated bypassing path if the request is allowed to bypass. A plurality of dependence lines are connected to the dependence controller for indicating a dependent status between at least two requests. The request may be allowed to bypass a stage even though the buffer of the stage is not empty. The method and mechanism of the present invention is capable of reducing the request transmission time by determining the dependence between the requests.

Abstract: A memory address remapping method is disclosed. The memory address remapping method comprises: providing a cache-related address having a tag, an associative tag, a set index and a block offset; providing a linear operator; performing a linear calculation with a first linear operator input and a second linear operator input to obtain a first output, wherein the first linear operator input is several bits picked from the set index of the cache-related address according to a quantity and a corresponding location of a plurality of bits in the location address of a memory address, such as DDR memory-related address, Rambus memory-related address, etc.

Abstract: The present invention relates to a quasi-synchronous multi-stage event synchronization apparatus by a phase lock loop (PLL) control circuit and a quasi-synchronous multi-stage synchronizer to tolerate clock uncertainty and speed up the synchronizing process between the asynchronous digital circuits from producing-end to consuming-end in the computer system. The phase lock loop (PLL) control circuit generates a pair of well-controlled clocks, PDU_CLK, CSM_CLK, assigned to producing-end and consuming-end and a pair of clock phase indicating signals, PDU_SYNC_PULSE, CSM_SYNC_PULSE, associated with the pair of well-controlled clocks. The quasi-synchronous multi-stage synchronizer routes the series of sync events into a synchronization stage with minimal synchronization delay from producing-end to consuming-end.

Abstract: A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request.