Patents by Inventor Tsan-Tang Chen

Tsan-Tang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230168141
    Abstract: A method for measuring steam pressure is provided, in which a steam pressure graph plotted according to temperature and strain is provided, so that the user can look up the steam pressure graph to know the steam pressure value inside a target object and determine whether there is a steam leakage in the target object.
    Type: Application
    Filed: November 30, 2022
    Publication date: June 1, 2023
    Inventors: Chian-Wei TZENG, Tsan-Tang CHEN, Xue-Wen YANG, Kwei-Yuan SU, Chuan-Sheng KAO, Sheng-Kai CHAN
  • Patent number: 10762951
    Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Tsai, Tsan-Tang Chen, Chung-Cheng Tsai, Yen-Hsueh Huang, Chang-Ting Lo, Chun-Yen Tseng, Yu-Tse Kuo
  • Patent number: 8743627
    Abstract: A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: June 3, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Shi-Wen Chen, Tsan-Tang Chen, Chi-Chang Shuai
  • Publication number: 20130182519
    Abstract: A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shi-Wen CHEN, Tsan-Tang Chen, Chi-Chang Shuai