Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.

Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

Abstract: A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. At least one wet cleaning process is performed to the recess and the substrate. Then, a baking process is performed to the recess and the substrate in an atmosphere containing H2 gas. After the baking process, a dry cleaning process is performed the recess and the substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.

Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a substrate; forming a gate structure on the substrate; forming a recess in the substrate at a lateral side of the gate structure; performing a pre-bake process at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr; and forming an epitaxial buffer layer in the recess.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a substrate; forming a gate structure on the substrate; forming a recess in the substrate at a lateral side of the gate structure; performing a pre-bake process at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr; and forming an epitaxial buffer layer in the recess.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a gate structure on the substrate; (c) performing a first deposition process to form a first epitaxial layer adjacent to the gate structure and performing a first etching process to remove part of the first epitaxial layer at the same time; and (d) performing a second etching process to remove part of the first epitaxial layer.

Abstract: A multilayer-stacked resistive random access memory device includes: first and second electrode layers; a resistive oxide layer which is electrically coupled to the first and second electrode layers, which exhibits resistive switching characteristics and which includes a metal oxide containing a first metal selected from the group consisting of W, Ti, Zr, Sn, Ta, Ni, Ag, Cu, Co, Hf, Ru, Mo, Cr, Fe, Al, and combinations thereof; and a sulfide layer contacting the resistive oxide layer and including a metal sulfide that contains a second metal that is the same as the first metal.

Abstract: A multilayer-stacked resistive random access memory device includes: first and second electrode layers; a resistive oxide layer which is electrically coupled to the first and second electrode layers, which exhibits resistive switching characteristics and which includes a metal oxide containing a first metal selected from the group consisting of W, Ti, Zr, Sn, Ta, Ni, Ag, Cu, Co, Hf, Ru, Mo, Cr, Fe, Al, and combinations thereof; and a sulfide layer contacting the resistive oxide layer and including a metal sulfide that contains a second metal that is the same as the first metal.

Abstract: A triangular warning sign for vehicles includes a triangular carrier board, a power supply and a mount. The triangular board is used for carrying a triangular warning sign and the power supply while the mount makes the triangular board stand perpendicular to the ground. The triangular warning sign is composed by electro luminescent pieces or a plurality of light-emitting diodes. The power supply can be solar power supply, batteries, or a car charger and it can automatically switch between the solar energy and batteries depending on occasions for providing the triangular warning sign power. In usage, the invention illuminates by Electro Luminescent or light-emitting diode to achieve features of electricity-saving, safety, and enough brightness for better warning effect, more convenience and energy-saving. The present invention can further disposed with an alarm and the power supply is with both AC and DC charging capabilities.