Patents by Inventor Tsao-Wen Lu
Tsao-Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9847138Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.Type: GrantFiled: March 4, 2016Date of Patent: December 19, 2017Assignee: AU OPTRONICS CORP.Inventors: Pei-Hua Chen, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Wei-Chun Hsu
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Publication number: 20160189798Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Pei-Hua CHEN, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Wei-Chun Hsu
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Patent number: 9318064Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.Type: GrantFiled: October 26, 2012Date of Patent: April 19, 2016Assignee: AU OPTRONICS CORPORATIONInventors: Pei-Hua Chen, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Wei-Chun Hsu
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Patent number: 8766899Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.Type: GrantFiled: April 14, 2011Date of Patent: July 1, 2014Assignee: AU Optronics Corp.Inventors: Wei-Chun Hsu, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Pei-Hua Chen
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Publication number: 20130141315Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.Type: ApplicationFiled: October 26, 2012Publication date: June 6, 2013Applicant: AU Optronics CorporationInventors: Pei-Hua Chen, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Wei-Chun Hsu
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Publication number: 20130141877Abstract: A fan-out circuit electrically connected to a driver and a plurality of signal lines is provided. The fan-out circuit includes a first fan-out trace including a first and a second conductive line, and a second fan-out trace including a third and a fourth conductive line. The second conductive line is connected between the first conductive line and one of the signal lines. The length of the second and fourth conductive lines are L1? and L2? respectively. An obtuse included angle is formed between the first and second conductive lines. The width of the first and third conductive lines is W1. The fourth conductive line is electrically connected to the third conductive line and another one of the signal lines. The obtuse included angle is formed between the third and fourth conductive lines. The width of the second and fourth conductive lines is W2, and (W2/L1?)>(W2/L2?) and L1?<L2?.Type: ApplicationFiled: April 12, 2012Publication date: June 6, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Chee-Wai Lau, Tsao-Wen Lu, Chien-Ju Lin, Chien-Hao Fu, Tsang-Hong Wang
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Patent number: 8305372Abstract: A display and a method for eliminating a residual image thereof are provided. The method includes detecting a status of an electric power supplied by a power supply unit of the display when the display is in the power on state; and coupling the electric power to a reference voltage when the electric power is suddenly terminated so as to accelerately discharge charges remaining on the electric power.Type: GrantFiled: June 23, 2009Date of Patent: November 6, 2012Assignee: Au Optronics CorporationInventors: Yu-Hsin Ting, Tsao-Wen Lu
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Publication number: 20120146962Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.Type: ApplicationFiled: April 14, 2011Publication date: June 14, 2012Inventors: Wei-Chun Hsu, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Pei-Hua Chen
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Publication number: 20120104402Abstract: In one aspect of the invention, an analog buffer circuit includes a p-channel field effect transistor (PTFT) and an n-channel field effect transistor (NTFT). Each of the PTFT and NTFT has a source region and a drain region defining a channel region therebetween, formed on a substrate such that the drain regions of the PTFT and the NTFT are in substantial contact with each other, a gate layer formed over and insulated from the corresponding channel region, a source electrode insulated from the gate layer and electrically connected to the corresponding source region, and a common drain electrode insulated from the gate layer and the source electrode, and is electrically connected to the drain regions of both the PTFT and the NTFT through a via defined over the depletion region.Type: ApplicationFiled: November 3, 2010Publication date: May 3, 2012Inventors: Pei-Hua Chen, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Wei-Chun Hsu
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Publication number: 20100277462Abstract: A display and a method for eliminating a residual image thereof are provided. The method includes detecting a status of an electric power supplied by a power supply unit of the display when the display is in the power on state; and coupling the electric power to a reference voltage when the electric power is suddenly terminated so as to accelerately discharge charges remaining on the electric power.Type: ApplicationFiled: June 23, 2009Publication date: November 4, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Yu-Hsin Ting, Tsao-Wen Lu