Patents by Inventor Tse-An CHEN

Tse-An CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071523
    Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kun-Tse Lee, Han-Sung Chen, Shih-Chang Huang
  • Patent number: 11915755
    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
  • Publication number: 20240063297
    Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tse-An CHEN, Lain-Jong LI, Wen-Hao CHANG, Chien-Chih TSENG
  • Publication number: 20240045539
    Abstract: A touch screen (500) can include electrodes (520, 540) (e.g., first and second touch electrodes, reference electrodes) on opposite sides (e.g., top and bottom) of a substrate (510). In some examples, vias (618, 638) can be used to couple the touch electrodes (520, 540) to conductive connections (518, 538) of flex circuits (502, 522) such that the connections (604, 624) to the flex circuits (502, 522) can be on the same side of the substrate (510) even if the touch electrodes (520, 540) are on opposite sides of the substrate (510). The conductive filling material of the via (618) can make direct contact with the conductive connections (604, 624) of the flex circuits (502, 522), for example.
    Type: Application
    Filed: December 9, 2020
    Publication date: February 8, 2024
    Inventors: Meng-Tse CHEN, Arnoldus Alvin BARLIAN, Bayu Atmaja THEDJOISWORO, Boris RUSS, Ziyang ZHANG, Nathan Krishan GUPTA
  • Patent number: 11863859
    Abstract: An electronic system including a display device, an image sensor, a face detection engine, an eye detection engine and an eye protection engine is provided. The image sensor captures an image. The face detection engine recognizes a user face in the image. The eye detection engine recognizes user eyes in the image. The eye protection engine turns off the display device when the user eyes are recognized in the image but the user face is not recognized in the image.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: January 2, 2024
    Inventors: Han-Chang Lin, Guo-Zhen Wang, Nien-Tse Chen
  • Patent number: 11847821
    Abstract: A method for training a deep learning network for face recognition includes: utilizing a face landmark detector to perform face alignment processing on at least one captured image, thereby outputting at least one aligned image; inputting the at least one aligned image to a teacher model to obtain a first output vector; inputting the at least one captured image a student model corresponding to the teacher module to obtain a second output vector; and adjusting parameter settings of the student model according to the first output vector and the second output vector.
    Type: Grant
    Filed: January 2, 2022
    Date of Patent: December 19, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Hao Chen, Shih-Tse Chen
  • Publication number: 20230384867
    Abstract: The present invention provides a motion detecting system, which includes a light source module, a plurality of image sensors and a control unit. The light source module illuminates at least one object. The image sensors respectively detect the object under the light emitted by the light source module to generate a plurality of detection results. The control unit is coupled to the image sensors, and generates a control command according to the detection results.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 30, 2023
    Inventors: TING-YANG CHANG, YEN-MIN CHANG, NIEN-TSE CHEN
  • Publication number: 20230378153
    Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20230369404
    Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Wei Shen, Tse-An Chen, Tung-Ying Lee, Lain-Jong Li
  • Publication number: 20230360913
    Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Tzu-Ang Chao, Gregory Michael Pitner, Tse-An Chen, Lain-Jong Li, Yu Chao Lin
  • Publication number: 20230352497
    Abstract: A display may have one or more bent portions. To increase the magnitude of curvature in a display and/or to allow for compound curvature in the display, a display panel may be partially formed in a planar state. The partial display panel is then bent to have desired curvature. After the partial display panel is bent, additional display components that are susceptible to damage during the bending process may be added to complete the display panel. A flexible printed circuit may be formed directly on the display panel using precise deposition of conductive material. By forming the flexible printed circuit layer-by-layer directly on the display panel, no substantive pressure needs to be applied to the display panel. Electrical connections may therefore be made to the display panel in regions of the display with high levels of curvature and/or with compound curvature without causing front-of-screen artifacts for the display panel.
    Type: Application
    Filed: March 1, 2023
    Publication date: November 2, 2023
    Inventors: Meng-Tse Chen, Anshi Liang, Arnoldus A Barlian, Bayu A Thedjoisworo, Boris A Russ, Chun-Hsien Lee, Chun-Lan Wu, Han-Chieh Chang, Jiming Yu, Marc J DeVincentis, Nathan K Gupta, Paolo Sacchetto, Paul S Drzaic, Zhen Zhang, Ziyang Zhang
  • Publication number: 20230343914
    Abstract: Conductive traces may be conformally wrapped around the side of a display panel that includes an array of display pixels. The conductive traces may electrically connect contacts on an upper surface of the display panel to corresponding contacts on a flexible printed circuit that is attached to a lower surface of the display panel. The side-wrapped conductive traces may be interposed between first and second insulating layers. The flexible printed circuit may have a multi-step interface that is electrically connected to the side-wrapped conductive traces. A system-in-package including a display driver integrated circuit may be mounted to the flexible printed circuit. The system-in-package may include a plurality of redistribution layers that electrically connect contacts on the display driver integrated circuit to contacts on the flexible printed circuit.
    Type: Application
    Filed: March 16, 2023
    Publication date: October 26, 2023
    Inventors: Han-Chieh Chang, Anshi Liang, Arnoldus A Barlian, Bayu A Thedjoisworo, Boris A Russ, Chun-Lan Wu, Ken Hsuan Liao, Marc J DeVincentis, Meng-Tse Chen, Nathan K Gupta, Paolo Sacchetto, Paul S Drzaic, Po-Jui Chen, Ying-Chih Wang, Yong Sun, Zhen Zhang, Ziyang Zhang
  • Patent number: 11800108
    Abstract: A method for image compression and a circuit system thereof are provided. In the method, pixel values of an image are obtained. A compression scenario is decided, for example, a uniform-quantization manner or a non-uniform-quantization manner is used for an M-bit image being compressed to an N-bit image so as to decide codeword sections for the image. Every codeword section has a codeword distance. The codeword sections have a fixed codeword distance in the uniform-quantization manner. Alternatively, in the non-uniform-quantization manner, the image can be divided into multiple codeword sections having different codeword distances according to a brightness distribution. Afterwards, a random number is generated for deciding codeword and index for original value of each of the pixels. An index table is accordingly formed. The index table is provided for obtaining the codeword in a decoding process by querying a codebook with the index.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: October 24, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wan-Ju Tang, Tsung-Hsuan Li, Shih-Tse Chen
  • Patent number: 11784225
    Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Wei Shen, Tse-An Chen, Tung-Ying Lee, Lain-Jong Li
  • Publication number: 20230317820
    Abstract: A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.
    Type: Application
    Filed: May 26, 2023
    Publication date: October 5, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG
  • Patent number: 11776945
    Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 11775076
    Abstract: The present invention provides a motion detecting system, which includes a light source module, a plurality of image sensors and a control unit. The light source module illuminates at least one object. The image sensors respectively detect the object under the light emitted by the light source module to generate a plurality of detection results. The control unit is coupled to the image sensors, and generates a control command according to the detection results.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: October 3, 2023
    Assignee: PIXART IMAGING INC.
    Inventors: Ting-Yang Chang, Yen-Min Chang, Nien-Tse Chen
  • Publication number: 20230307391
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Application
    Filed: May 29, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Publication number: 20230307234
    Abstract: The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tse-An CHEN, Lain-Jong LI
  • Publication number: 20230291317
    Abstract: A multi-mode hybrid control DC-DC converting circuit has a switching power converter and a microcontroller. The switching power converter has a transformer and a switching switch. The switching switch is connected to a primary-side winding of the transformer in series. The microcontroller is connected to the switching power converter and a control terminal of the switching switch. The microcontroller sets multiple thresholds according to an input voltage of the switching power converter, and determines whether a feedback voltage of the switching power converter is higher or lower than each one of the thresholds to perform a variable-frequency mode, a constant-frequency mode, or a pulse-skipping mode. The microcontroller outputs a driving signal to the switching switch and correspondingly adjusts a frequency of the driving signal according to the variable-frequency mode, the constant-frequency mode, or the pulse-skipping mode which is performed.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 14, 2023
    Applicant: MINMAX TECHNOLOGY CO., LTD.
    Inventors: CHENG-CHOU WU, CHUN-TSE CHEN