Abstract: A method includes accessing a layout of a first die, wherein the first die is of a three-dimensional integrated circuit (3DIC) structure; generating a virtual design based on the layout of the first die, a first resistance and capacitance (RC) technology file (techfile) of the first die, and a second RC techfile of a second die, wherein the second die is of the 3DIC structure; performing a virtual coupling capacitance extraction on the virtual design to form a virtual coupling capacitance netlist; performing an static timing analysis on the first die with the virtual coupling capacitance netlist.

Abstract: An IC device includes a first and second stacked transistor structures including respective first and second and third and fourth transistors in a semiconductor substrate, first and second bit lines and a word line on one of a front or back side of the semiconductor substrate, and a power supply line on the other of the front or back side. The first transistor includes a source/drain (S/D) terminal electrically connected to the first bit line, a S/D terminal electrically connected to a S/D terminal of the second transistor, and a gate electrically connected to the word line, the third transistor includes a S/D terminal electrically connected to the second bit line, a S/D terminal electrically connected to a S/D terminal of the fourth transistor, and a gate electrically connected to the word line, and the second and fourth transistors include S/D terminals electrically connected to the power supply line.

Abstract: An integrated circuit (IC) device includes a plurality of memory segments. Each memory segment includes a plurality of memory cells, and a local bit line electrically coupled to the plurality of memory cells and arranged on a first side of the IC device. The IC device further includes a global bit line electrically coupled to the plurality of memory segments, and arranged on a second side of the IC device. The second side is opposite the first side in a thickness direction of the IC device.

Abstract: An acoustic wave device includes: a substrate; a first electrode on the substrate; a piezoelectric layer on the first electrode; and a second electrode on the piezoelectric layer. A bonding interface is located between the substrate and the first electrode. The full width at half maximum (FWHM) in the X-ray diffraction pattern of the crystal plane <002> of the piezoelectric layer is between 10 arc-sec and 3600 arc-sec.

Abstract: The present disclosure provides a self-rectifying RRAM cell structure including a first electrode layer formed of a nitride of a first metal element, a second electrode layer formed of a second metal element that is different from the first metal element, a first resistive switching layer and a second resistive switching layer. The first resistive switching layer is sandwiched between the first electrode layer and the second resistive switching layer, and the second resistive switching layer is sandwiched between the first resistive switching layer and the second electrode layer. The first resistive switching layer has a first bandgap that is lower than the second bandgap of the second resistive switching layer. Furthermore, a RRAM 3D crossbar array architecture is also provided.

Abstract: A self-rectifying resistive random access memory (RRAM) cell structure is provided. The self-rectifying RRAM cell structure includes a first electrode. An insulator-metal-transition (IMT) material layer is disposed on the first electrode. A barrier layer is disposed on the IMT material layer. A second electrode is disposed on the barrier layer. The IMT material layer is separated from the second electrode by the barrier layer.

Abstract: A self-rectifying resistive random access memory (RRAM) cell structure is provided. The self-rectifying RRAM cell structure includes a first electrode. An insulator-metal-transition (IMT) material layer is disposed on the first electrode. A barrier layer is disposed on the IMT material layer. A second electrode is disposed on the barrier layer. The IMT material layer is separated from the second electrode by the barrier layer.

Abstract: The present disclosure provides a self-rectifying RRAM cell structure including a first electrode layer formed of a nitride of a first metal element, a second electrode layer formed of a second metal element that is different from the first metal element, a first resistive switching layer and a second resistive switching layer. The first resistive switching layer is sandwiched between the first electrode layer and the second resistive switching layer, and the second resistive switching layer is sandwiched between the first resistive switching layer and the second electrode layer. The first resistive switching layer has a first bandgap that is lower than the second bandgap of the second resistive switching layer. Furthermore, a RRAM 3D crossbar array architecture is also provided.

Abstract: A polylactic acid composition includes polylactic acid, and a biodegradable nucleating polymer in an amount from 0.1 to 10 wt %, based on the total weight of the polylactic acid composition. The biodegradable nucleating polymer is used as a nucleating agent, and is selected from the group of aliphatic polyester other than polylactic acid, aliphatic-aromatic copolyester, and polyethylene glycol.

Abstract: A computer-implemented method and system for automating control of a furnace area within a semiconductor fabrication facility are provided. In one example, the method includes processing a current batch using process equipment, removing the current batch from the process equipment, and loading a next batch into the process equipment. The current batch may then be tested to determine if the current batch was properly processed. If the current batch fails the testing, the next batch may be removed from the process equipment and corrections may be made to the process equipment before reloading the next batch. If the current batch passes the testing, the next batch may be set as the new current batch and the new current batch may be processed.