Abstract: A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.

Abstract: A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.

Abstract: A hybrid micro-circuit device has multiple layers overlying a printed circuit board (PCB), including a first semiconductor chip component that is electrically connected to the PCB, and a second semiconductor chip component that is electrically connected to first semiconductor chip component. A molding compound surrounds the stack of components that includes the semiconductor chip components. This molding compound may include pillars that are higher than the height of the stacked components. The pillars of molded material may be configured to receive most of the stress from other components over the stacked components. The pillars of molded material may also help define a recess between the stack components and the other components that overlie the stacked components, where a thermal interface material (TIM) may be located. Further, there may be an air gap between parts of the semiconductor chip components.

Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract: An adaptive interposer is provided to be operably disposable between first and second solder materials of first and second electronic devices, respectively. The adaptive interposer includes a plate element formed to define cavities and third solder material disposable in the cavities to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second solder materials.

Abstract: A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.

Abstract: A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.

Abstract: An adaptive interposer is provided to be operably disposable between first and second solder materials of first and second electronic devices, respectively. The adaptive interposer includes a plate element formed to define cavities and third solder material disposable in the cavities to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second solder materials.

Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract: A sealed package having a device disposed on a wafer structure and slid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract: A flip-chip mounted semiconductor structure having a flip chip mounting pad and a circuit structure flip-chip mounted to the flip chip mounting pad. The circuit structure includes: a semiconductor die; and a stiffener structure attached to the die, the stiffener structure having a conduit passing through the stiffener structure between a front side of the stiffener structure and a hack side of the stiffener structure, the stiffener and attached die having a degree of rigidity greater than the die alone.

Abstract: A wafer assembly with internal fluid channels. The assembly is fabricated by creating one or more channels in a first surface of a first semiconductor wafer and creating an oxide surface on the first surface of the first semiconductor wafer. An oxide surface is also created on a first surface of a second semiconductor wafer. The assembly is fabricated by bonding the oxide surface of the first surface of the first semiconductor wafer to the oxide surface of the first surface of the second semiconductor wafer to create a wafer assembly and to seal the one or more channels at edges defined by the bonded first and second surfaces.

Abstract: A wafer assembly with internal fluid channels. The assembly is fabricated by creating one or more channels in a first surface of a first semiconductor wafer and creating an oxide surface on the first surface of the first semiconductor wafer. An oxide surface is also created on a first surface of a second semiconductor wafer. The assembly is fabricated by bonding the oxide surface of the first surface of the first semiconductor wafer to the oxide surface of the first surface of the second semiconductor wafer to create a wafer assembly and to seal the one or more channels at edges defined by the bonded first and second surfaces.

Abstract: In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Abstract: In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Abstract: A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Abstract: A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Abstract: An antenna array is assembled by direct attaching a flip chip transmit/receive (T/R) module to an antenna circuit board. A fillet bond is applied to the circuit board and the flip chip T/R module around at least a portion of the periphery of the flip chip T/R module.

Abstract: A spring-loaded ball contact device having a housing, a spring disposed in the housing, a moveable plunger disposed in the housing that contacts the spring, a freely moveable ball contact disposed at an end of the plunger, and a lubricant stored within the housing for lubricating the ball contact. A rotary connector using the spring-loaded ball contact devices has first and second printed wiring boards that rotate relative to each other that are electrically interconnected using a plurality of spring-loaded ball contact devices disposed on the first printed wiring board. The spring-loaded ball contact devices are used to transfer electrical signals or power to conductive contacts formed on the second printed wiring board.