Patents by Inventor Tse-Hua Lu

Tse-Hua Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955389
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Publication number: 20240072079
    Abstract: A method for forming an isolation structure includes following operations. A trench is formed in a semiconductor substrate. A first insulating layer covering a bottom and sidewalls of the trench is formed. A charge-trapping layer is formed on the first insulating layer. The trench is filled with a second insulating layer. The charge-trapping layer include a material different from those of the first insulating layer and the second insulating layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: TZUNG-YI TSAI, KUO-YU WU, TSE-HUA LU
  • Patent number: 11894404
    Abstract: The present disclosure provides an optical structure and a method for fabricating an optical structure, the method includes forming a light detection region in a substrate, forming an isolation structure at surrounding the light detection region, and forming a primary grid over the isolation structure, including forming a metal layer over the isolation structure, forming a first dielectric layer over the metal layer, and partially removing the metal layer and the first dielectric layer with a first mask by patterning, and forming a secondary grid at least partially surrounded by the primary grid laterally.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
  • Patent number: 11848339
    Abstract: A semiconductor structure includes a semiconductor substrate, an image sensor, and an isolation structure. The isolation structure is adjacent to the image sensor and disposed in the semiconductor substrate. The isolation structure includes a first oxide layer, a second oxide layer over the first oxide layer, and a charge-trapping layer disposed between the first oxide layer and the second oxide layer. The charge-trapping layer includes a material different from those of the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzung-Yi Tsai, Kuo-Yu Wu, Tse-Hua Lu
  • Publication number: 20230352507
    Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Ming-Shiang Lin, Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
  • Publication number: 20230307479
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a substrate having a first side and a second side. The substrate includes a pixel region. A photodetector is in the pixel region. A first doped region is in the pixel region. A second doped region is in the pixel region. The second doped region is vertically between the first doped region and the first side of the substrate. A doped well is in the substrate and laterally surrounds the pixel region. The doped well is partially in the second doped region. A portion of the second doped region is vertically between the doped well and the second side of the substrate. A trench isolation structure is in the semiconductor substrate and laterally surrounds the pixel region. A footprint of the trench isolation structure is within a footprint of the doped well.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 28, 2023
    Inventors: Yen-Yu Chen, Yen-Ting Chiang, Bai-Tao Huang, Tse-Hua Lu, Tzu-Hsuan Hsu, Shyh-Fann Ting, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 11749700
    Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substrate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Shiang Lin, Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
  • Publication number: 20230017723
    Abstract: A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Inventors: MING-SHIANG LIN, TZUNG-YI TSAI, WAN-LIN CHIANG, HONG-PING LUO, KUO-YU WU, TSE-HUA LU
  • Publication number: 20220367295
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Patent number: 11482459
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Publication number: 20220302190
    Abstract: A semiconductor structure includes a semiconductor substrate, an image sensor, and an isolation structure. The isolation structure is adjacent to the image sensor and disposed in the semiconductor substrate. The isolation structure includes a first oxide layer, a second oxide layer over the first oxide layer, and a charge-trapping layer disposed between the first oxide layer and the second oxide layer. The charge-trapping layer includes a material different from those of the first oxide layer and the second oxide layer.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: TZUNG-YI TSAI, KUO-YU WU, TSE-HUA LU
  • Publication number: 20220293654
    Abstract: The present disclosure provides an optical structure and a method for fabricating an optical structure, the method includes forming a light detection region in a substrate, forming an isolation structure at surrounding the light detection region, and forming a primary grid over the isolation structure, including forming a metal layer over the isolation structure, forming a first dielectric layer over the metal layer, and partially removing the metal layer and the first dielectric layer with a first mask by patterning, and forming a secondary grid at least partially surrounded by the primary grid laterally.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 15, 2022
    Inventors: YUN-HAO CHEN, KUO-YU WU, TSE-HUA LU
  • Patent number: 11348958
    Abstract: The present disclosure provides an optical structure, including a substrate, a light detection region in the substrate, an isolation structure in the substrate, surrounding the light detection region, a color filter layer over the substrate, and a dielectric grid structure in the color filter layer, the dielectric grid structure overlapping with the light detection region.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
  • Publication number: 20210375970
    Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substrate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.
    Type: Application
    Filed: April 16, 2021
    Publication date: December 2, 2021
    Inventors: Ming-Shiang LIN, Yun-Hao CHEN, Kuo-Yu WU, Tse-Hua LU
  • Publication number: 20210035974
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Publication number: 20200365636
    Abstract: The present disclosure provides an optical structure, including a substrate, a light detection region in the substrate, an isolation structure in the substrate, surrounding the light detection region, a color filter layer over the substrate, and a dielectric grid structure in the color filter layer, the dielectric grid structure overlapping with the light detection region.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: YUN-HAO CHEN, KUO-YU WU, TSE-HUA LU
  • Patent number: 10833082
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Publication number: 20200043925
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Patent number: 10504896
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Tse-Hua Lu
  • Patent number: 10269840
    Abstract: The image sensing device includes a pixel region in a pixel array area and a dummy pixel region in a periphery area. The pixel region includes a radiation region, a floating diffusion region, a transfer transistor, a source-follower transistor, a reset transistor and a select transistor. The dummy pixel region includes a radiation region and a floating diffusion region. A gate of one of the transfer transistor, the reset transistor and the select transistor in the pixel region is electrically connected to the radiation region or the floating diffusion region in the dummy pixel region.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Chi Hung, Jen-Cheng Liu, Ching-Chun Wang, Tse-Hua Lu