Abstract: An all-digital duty cycle corrector and a method for correcting a duty cycle of an output clock are provided. The all-digital duty cycle corrector includes a duty cycle adjustment circuit, an asynchronous sampler, a counter and a correction control circuit. The duty cycle adjustment circuit performs duty cycle adjustment on an input clock to generate the output clock according to a digital control code. The asynchronous sampler performs asynchronous sampling on the output clock to generate N sampling results at N time points, respectively. The counter counts a number of first logic values among the N sampling results to generate a counting result. The correction control circuit compares the counting result with a reference value to generate a comparison result, and selectively adjusts the digital control code according to the comparison result, in order to correct the duty cycle of the output clock.

Abstract: A noise detection circuit includes an analog-to-digital conversion (ADC) circuit and a noise event recognition circuit. The ADC circuit is configured to convert an analog signal outputted from a device under test (DUT) into a sequence of digital codes. The noise event recognition circuit, coupled to the ADC circuit, is configured to determine a noise count of the sequence of digital codes, and refer to the noise count to determine if a noise event occurs in the DUT. The noise count indicates a number of times a change in code values between two successive digital codes exceeds a predetermined value.

Abstract: A noise detection circuit includes an analog-to-digital conversion (ADC) circuit and a noise event recognition circuit. The ADC circuit is configured to convert an analog signal outputted from a device under test (DUT) into a sequence of digital codes. The noise event recognition circuit, coupled to the ADC circuit, is configured to determine a noise count of the sequence of digital codes, and refer to the noise count to determine if a noise event occurs in the DUT. The noise count indicates a number of times a change in code values between two successive digital codes exceeds a predetermined value.