Patents by Inventor Tse-Main Kuo

Tse-Main Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6812487
    Abstract: A test key for validating the doping concentration of buried layers within a deep trench capacitor. The test key is deposited in the scribe line region of a wafer. In the test key of the present invention, the deep trench capacitor is deposited in the scribe line region and has three buried layers of three doping concentrations. An isolation region is deposited in the capacitor, and a first plug, a second and a third plug are coupled to three positions of one buried layer of the three respectively. The present invention determines whether the doping concentration of buried layers within a deep trench capacitor is valid by a first resistance measured between the first plug and the second plug and a second resistance measured between the second plug and the third plug.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: November 2, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Tie-Jiang Wu, Chien-Chang Huang, Yu-Wei Ting, Bo-Ching Jiang, Tse-Main Kuo
  • Patent number: 6788598
    Abstract: A test key disposed on a scribe line of a wafer. The test key includes: two active areas disposed on the substrate; two first deep trench capacitors disposed on the substrate outside the two active areas; a rectangular active word line disposed on the substrate covering the first deep trench capacitors and the active areas; first and second passing word lines disposed on one side of the rectangular active word line and across the parallel active areas; a third passing word line disposed on another side of the rectangular active word line and across another end of the two active areas; two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas; and four contacts disposed on the first active areas between the first and second word lines and between the third and the rectangular active word line.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: September 7, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Tie-Jiang Wu, Jeng-Ping Lin, Tse-Main Kuo, Hsu-Cheng Fan
  • Publication number: 20040017710
    Abstract: A test key disposed on a scribe line of a wafer. The test key includes: two active areas disposed on the substrate; two first deep trench capacitors disposed on the substrate outside the two active areas; a rectangular active word line disposed on the substrate covering the first deep trench capacitors and the active areas; first and second passing word lines disposed on one side of the rectangular active word line and across the parallel active areas; a third passing word line disposed on another side of the rectangular active word line and across another end of the two active areas; two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas; and four contacts disposed on the first active areas between the first and second word lines and between the third and the rectangular active word line.
    Type: Application
    Filed: May 30, 2003
    Publication date: January 29, 2004
    Applicant: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Tie-Jiang Wu, Jeng-Ping Lin, Tse-Main Kuo, Hsu-Cheng Fan