Patents by Inventor Tse SU
Tse SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908790Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.Type: GrantFiled: January 6, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li Yang, Po-Hao Tsai, Ching-Wen Hsiao, Hong-Seng Shue, Yu-Tse Su
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Patent number: 11742576Abstract: A tunable antenna module includes a ground metal plane, a nonconductive support element, a first radiation metal element, a second radiation metal element, a switch element, and a plurality of impedance elements. The ground metal plane provides a ground voltage. The first radiation metal element is coupled to a signal source. The second radiation metal element is adjacent to and separate from the first radiation metal element. The switch element selects one of the impedance elements, such that the second radiation metal element is coupled through the selected impedance element to the ground voltage. The nonconductive support element has a 3D (Three-Dimensional) structure. The first radiation metal element and the second radiation metal element are distributed over the nonconductive support element.Type: GrantFiled: November 23, 2020Date of Patent: August 29, 2023Assignee: WISTRON NEWEB CORP.Inventors: Tse Su, Chung-Yen Hsiao, Huang-Tse Peng
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Publication number: 20230065794Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Hong-Seng SHUE, Ming-Da CHENG, Ching-Wen HSIAO, Yao-Chun CHUANG, Yu-Tse SU, Chen-Shien CHEN
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Publication number: 20220367347Abstract: A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li YANG, Po-Hao TSAI, Ching-Wen HSIAO, Hong-Seng SHUE, Yu-Tse SU
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Publication number: 20220216143Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.Type: ApplicationFiled: January 6, 2021Publication date: July 7, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li YANG, Po-Hao TSAI, Ching-Wen HSIAO, Hong-Seng SHUE, Yu-Tse SU
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Patent number: 11329008Abstract: A method for manufacturing a semiconductor package includes following operations. A die having a first surface and a second surface opposite to the first surface is provided. A polymeric film is disposed over the second surface of the die. An adhesive film is provided. The die and the polymeric film are attached to a carrier substrate through the adhesive film. The die, the polymeric film and the adhesive film are molded with a molding compound. The polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate.Type: GrantFiled: September 22, 2020Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Shien Chen, Ming-Da Cheng, Ming-Chih Yew, Yu-Tse Su
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Publication number: 20220050940Abstract: Embodiments of the present disclosure provide a method and a system for optimizing metal stamping process parameters, thereby performing die parameters optimization and stamping forming curve optimization to achieve various design goals. Embodiments of the present disclosure automatically model the die parameters and stamping forming curves, and import them into an optimization process. Embodiments of the present disclosure use a response surface method to fit a linear polynomial function, and then perform optimization on a response surface to obtain a best die parameters values combination and a best stamping forming curve.Type: ApplicationFiled: September 29, 2020Publication date: February 17, 2022Inventors: Ching-Hua HSIEH, Hui-Chi CHANG, Po-Tse SU, Pin-Jyun CHEN, Fu-Chuan HSU
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Publication number: 20210257734Abstract: A tunable antenna module includes a ground metal plane, a nonconductive support element, a first radiation metal element, a second radiation metal element, a switch element, and a plurality of impedance elements. The ground metal plane provides a ground voltage. The first radiation metal element is coupled to a signal source. The second radiation metal element is adjacent to and separate from the first radiation metal element. The switch element selects one of the impedance elements, such that the second radiation metal element is coupled through the selected impedance element to the ground voltage. The nonconductive support element has a 3D (Three-Dimensional) structure. The first radiation metal element and the second radiation metal element are distributed over the nonconductive support element.Type: ApplicationFiled: November 23, 2020Publication date: August 19, 2021Inventors: Tse SU, Chung-Yen HSIAO, Huang-Tse PENG
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Publication number: 20210013158Abstract: A method for manufacturing a semiconductor package includes following operations. A die having a first surface and a second surface opposite to the first surface is provided. A polymeric film is disposed over the second surface of the die. An adhesive film is provided. The die and the polymeric film are attached to a carrier substrate through the adhesive film. The die, the polymeric film and the adhesive film are molded with a molding compound. The polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate.Type: ApplicationFiled: September 22, 2020Publication date: January 14, 2021Inventors: CHEN-SHIEN CHEN, MING-DA CHENG, MING-CHIH YEW, YU-TSE SU
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Patent number: 10867976Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: GrantFiled: December 11, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Patent number: 10797005Abstract: A semiconductor package includes a die including a first surface and a second surface opposite to the first surface, a warpage control unit disposed over the second surface of the die and entirely overlapping the second surface of the die, and a molding compound surrounding the die and the warpage control unit. The warpage control unit includes an adhesive portion disposed over the second surface of the die and a warpage adjustable portion sandwiched between the adhesive portion and the die.Type: GrantFiled: February 21, 2018Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Shien Chen, Ming-Da Cheng, Ming-Chih Yew, Yu-Tse Su
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Publication number: 20200118984Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Patent number: 10510734Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: GrantFiled: November 30, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Publication number: 20190164907Abstract: A semiconductor package includes a die including a first surface and a second surface opposite to the first surface, a warpage control unit disposed over the second surface of the die and entirely overlapping the second surface of the die, and a molding compound surrounding the die and the warpage control unit. The warpage control unit includes an adhesive portion disposed over the second surface of the die and a warpage adjustable portion sandwiched between the adhesive portion and the die.Type: ApplicationFiled: February 21, 2018Publication date: May 30, 2019Inventors: CHEN-SHIEN CHEN, MING-DA CHENG, MING-CHIH YEW, YU-TSE SU
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Patent number: 10276548Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: GrantFiled: August 4, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Publication number: 20190115326Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: ApplicationFiled: November 30, 2018Publication date: April 18, 2019Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Publication number: 20180076184Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: ApplicationFiled: August 4, 2017Publication date: March 15, 2018Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen