Abstract: A multi-core processing device includes a first processor core and a second processor core. The computation capability of the second processor core is greater than that of the first processor core. When loading of a task is lower than an hmp_down_migration threshold, the multi-core processing device allocates the task to the first processor core. When the loading of a task is higher than an hmp_up_migration threshold, the multi-core processing device allocates the task to the second processor core. At least one of the hmp_down_threshold and the hmp_up_threshold changes from a first value to a second value during a run time of the multi-core processing device.

Abstract: A multi-core processing device includes a first processor core and a second processor core. The computation capability of the second processor core is greater than that of the first processor core. When loading of a task is lower than an hmp_down_migration threshold, the multi-core processing device allocates the task to the first processor core. When the loading of a task is higher than an hmp_up_migration threshold, the multi-core processing device allocates the task to the second processor core. At least one of the hmp_down_threshold and the hmp_up_threshold changes from a first value to a second value during a run time of the multi-core processing device.

Abstract: A multi-standard video decoding system comprises a memory, a multi-master bridge interface, a peer-to-peer bus, a plurality of processors and a plurality of hardware accelerators. The memory stores bit stream and temporal data produced during decoding flow. The multi-master bridge interface is connected to the memory. At least one of the plurality of processors receives bit streams from the memory via the multi-master bridge interface. Each of the plurality of hardware accelerators receives instructions from one of the plurality of the processors and operates related video decoding flow, and accesses the memory via the multi-master bridge interface. The peer-to-peer bus connects the plurality of processors and the plurality of hardware accelerators.