Abstract: A memory device includes a main memory, a first sub-memory and a controller. When the first sub-memory is erased, the first sub-memory generates a first erase completion signal. The controller receives an erase signal to erase the main memory. The controller performs an erase operation on the main memory according to the erase signal and the first erase completion signal.

Abstract: A control circuit including a quadrature encoder circuit, a counter circuit, and a cutoff circuit is provided. The quadrature encoder circuit generates a first edge signal and a first direction signal according to a first external signal and a second external signal. The counter circuit performs a counting operation according to the first edge signal and the first direction signal. In response to the timer signal being enabled, the cutoff circuit prevents the first edge signal and the first direction signal from entering the counter circuit and provides a second edge signal and a second direction signal to the counter circuit so that the counter circuit performs the counting operation according to the second edge signal and the second direction signal.

Abstract: A memory-control circuit for use in an integrated circuit is provided. The memory-control circuit includes a memory controller and a timer circuit. The memory controller performs an erase operation on a target data block of the flash memory according to an erase command from a processor, and generates an erase signal. The timer circuit starts a counting operation in response to the erase signal. In response to an intellectual-property-core circuit generating an interrupt signal, the memory controller and the timer circuit respectively suspend the erase operation and the counting operation. In response to the interrupt signal being cleared, the memory controller and the timer circuit respectively resume the erase operation and the counting operation. In response to the timer circuit having counted up to a predetermined value, the timer circuit outputs a completion signal to the memory controller to indicate that the erase operation is complete.

Abstract: A data-receiving circuit adapted to an electronic device is provided herein. The electronic device receives a power-saving signal to operate in a power-saving mode. The data-receiving circuit includes a first register, a second register, a decoder, a data register, and a control circuit. The first register is configured to store a target value. The second register is configured to store the length of the target value. The decoder captures control data and endpoint data from an IR signal. The data register is configured to store the control data. The control circuit empties out the data register according to the power-saving signal and the endpoint signal.

Abstract: The disclosure provides a signal synchronizing device and a digital signal output device. A digital circuit counts a first frequency signal to generate a count value, and generates an output voltage according to the count value. An analog circuit generates a feedback signal according to the output voltage. A synchronization circuit samples the feedback signal according to a second frequency signal to generate a synchronization signal. A control circuit generates a voltage control signal according to the second frequency signal and the synchronization signal to control the digital circuit to stop counting the first frequency signal, and a frequency of the first frequency signal is lower than a frequency of the second frequency signal.

Abstract: A data-receiving circuit adapted to an electronic device is provided herein. The electronic device receives a power-saving signal to operate in a power-saving mode. The data-receiving circuit includes a first register, a second register, a decoder, a data register, and a control circuit. The first register is configured to store a target value. The second register is configured to store the length of the target value. The decoder captures control data and endpoint data from an IR signal. The data register is configured to store the control data. The control circuit empties out the data register according to the power-saving signal and the endpoint signal.