Patents by Inventor Tse-Yuh Yeh

Tse-Yuh Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Combined buffer for snoop, store merging, load miss, and writeback operations
    Patent number: 7398361
    Abstract: In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: July 8, 2008
    Assignee: P.A. Semi, Inc.
    Inventors: Ramesh Gunna, Po-Yung Chang, Sridhar P. Subramanian, James B. Keller, Tse-Yuh Yeh
  • Combined buffer for snoop, store merging, load miss, and writeback operations
    Publication number: 20070050564
    Abstract: In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 1, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Ramesh Gunna, Po-Yung Chang, Sridhar Subramanian, James Keller, Tse-Yuh Yeh