Patents by Inventor Tsei-Chung Fu
Tsei-Chung Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11515288Abstract: A method includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.Type: GrantFiled: July 21, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
-
Publication number: 20200350280Abstract: A method includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
-
Patent number: 10748869Abstract: A method includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.Type: GrantFiled: March 28, 2018Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
-
Patent number: 10636748Abstract: A package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.Type: GrantFiled: June 15, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
-
Patent number: 10224293Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.Type: GrantFiled: April 24, 2017Date of Patent: March 5, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
-
Patent number: 10163818Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.Type: GrantFiled: April 24, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
-
Publication number: 20180301424Abstract: A package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.Type: ApplicationFiled: June 15, 2018Publication date: October 18, 2018Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
-
Patent number: 10083913Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.Type: GrantFiled: October 3, 2016Date of Patent: September 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
-
Publication number: 20180219000Abstract: In accordance with a method embodiment includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.Type: ApplicationFiled: March 28, 2018Publication date: August 2, 2018Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
-
Patent number: 9941244Abstract: In accordance with a method embodiment includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.Type: GrantFiled: December 9, 2013Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
-
Patent number: 9847269Abstract: An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.Type: GrantFiled: July 31, 2015Date of Patent: December 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Jeffrey Chang, Chun-Hsing Su, Tsei-Chung Fu, Yi-Chao Mao
-
Patent number: 9741693Abstract: The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.Type: GrantFiled: November 12, 2015Date of Patent: August 22, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Fu Kao, Tsei-Chung Fu, Jing-Cheng Lin
-
Publication number: 20170229404Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
-
Publication number: 20170141079Abstract: The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.Type: ApplicationFiled: November 12, 2015Publication date: May 18, 2017Inventors: CHIN-FU KAO, TSEI-CHUNG FU, JING-CHENG LIN
-
Patent number: 9633924Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.Type: GrantFiled: December 16, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
-
Publication number: 20170033063Abstract: An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng Lin, Jeffrey Chang, Chun-Hsing Su, Tsei-Chung Fu, Yi-Chao Mao
-
Publication number: 20170025359Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.Type: ApplicationFiled: October 3, 2016Publication date: January 26, 2017Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
-
Publication number: 20160307871Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
-
Patent number: 9461018Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.Type: GrantFiled: April 17, 2015Date of Patent: October 4, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
-
Patent number: 9358660Abstract: A grinding wheel includes a base disk, and a plurality of teeth protruding beyond a surface of the base disk. The plurality of teeth is aligned to an elongated ring encircling a center of the grinding wheel.Type: GrantFiled: May 29, 2015Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsing Su, Jing-Cheng Lin, Tsei-Chung Fu, Wen-Hua Chang, Yi-Chao Mao