Abstract: A distributed shared memory multi-processor system includes a System Control Unit (SCU) which is made up of a system control unit address section (SCUA) and system control unit data sections (SCUDs). The SCU is scalable by dividing the control and data flow functions of the SCU, and then parallelizing the data path. This allows the number of processors in the system to be increased or higher performance processors to be added by increasing the number of SCUDs and reprogramming crossbar switches incorporated in the SCUA and SCUDs. This results in the overall increase of the multi-processor system performance.

Abstract: A network of integrated communication switches and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor computer architecture. The nodes contain multiple processors operatively connected to associated memory units through memory controllers. The communication switches and coherence controllers has associated coherence directories which maintain coherence information for all memory lines that are “homed” in the nodes that are directly connected to the particular communication switch and coherence controller.