Abstract: An integrated circuit process includes the following steps. A substrate including a flash cell area and a logic area is provided. A first sacrificial gate on the substrate of the flash cell area and a second sacrificial gate on the substrate of the logic area are formed, and a dielectric layer covers the substrate beside the first sacrificial gate and the second sacrificial gate. The first sacrificial gate is removed to forma first recess in the dielectric layer. An oxide/nitride/oxide layer is formed to conformally cover surfaces of the first recess. An integrated circuit formed by said integrated circuit process is also provided.

Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.