Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

Abstract: The present invention provides a transistor comprising a substrate having a surface; a first deep well region in the substrate; a second deep well region in the substrate, isolated from and encircling the first deep well region; a first well region in the substrate and on the first deep well region; two second well regions in the second deep well region and respectively at two opposite sides of the first well region; a source region in the first well region and adjacent to the surface; two drain regions in the two second well regions respectively and adjacent to the surface; two gate structures on the surface, wherein each of the two gate structures is between the source region and one of the drain regions respectively; and a guard ring in the substrate encircling the second deep well region, and on the periphery of the transistor.

Abstract: The present invention provides a transistor comprising a substrate having a surface; a first deep well region in the substrate; a second deep well region in the substrate, isolated from and encircling the first deep well region; a first well region in the substrate and on the first deep well region; two second well regions in the second deep well region and respectively at two opposite sides of the first well region; a source region in the first well region and adjacent to the surface; two drain regions in the two second well regions respectively and adjacent to the surface; two gate structures on the surface, wherein each of the two gate structures is between the source region and one of the drain regions respectively; and a guard ring in the substrate encircling the second deep well region, and on the periphery of the transistor.

Abstract: The present invention provides a semiconductor device structure which integrates a lateral diffused metal oxide semiconductor (LDMOS) with a Schottky diode, including: a substrate, having a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region having a second conductivity type complementary to the first conductivity type, a source region formed in the substrate, the source region having the second conductivity type, a high-voltage well region formed in the substrate, the high-voltage well region having a first conductivity type; a Schottky diode disposed on the substrate and disposed beside the LDMOS, wherein the semiconductor device structure is an asymmetric structure, and a deep well region disposed in the substrate and having the second conductivity type, wherein the LDMOS and the Schottky diode are all formed within the deep well region.

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Abstract: A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region.

Abstract: A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region.