Abstract: A capacitor charging circuit is provided with a primary side output voltage sensing circuit including an RC network having an RC time constant with a predetermined relationship to the RC time constant of the output capacitor. Once the capacitor voltage reaches a fully charged level, the charging mode is terminated. The output voltage is continuously detected by measuring the voltage across the primary side RC network that decays at a predetermined rate with respect to the output capacitor and the charging mode is commenced once the RC voltage falls to a predetermined level. According to a further aspect of the invention, a switch control circuit in a flyback converter controls the switch off time in response to detection of a change in the slope polarity of the voltage at a terminal of the switch.

Abstract: A capacitor charging circuit is provided with a primary side output voltage sensing circuit including an RC network having an RC time constant with a predetermined relationship to the RC time constant of the output capacitor. Once the capacitor voltage reaches a fully charged level, the charging mode is terminated. The output voltage is continuously detected by measuring the voltage across the primary side RC network that decays at a predetermined rate with respect to the output capacitor and the charging mode is commenced once the RC voltage falls to a predetermined level. According to a further aspect of the invention, a switch control circuit in a flyback converter controls the switch off time in response to detection of a change in the slope polarity of the voltage at a terminal of the switch.

Abstract: Sampling noise in an analog signal output from a codec, such as a speech codec, is reduced using linear interpolation. The output of a codec is input into two sample and hold circuits. The circuits generate two output signals (i.e. voltages) for each input signal. One of the output signals represents an interpolated signal located midway between an historical output signal and input signal. The generation of interpolated output signals reduces sampling noise.

Abstract: An integrated circuit comprising a balanced differential amplifier. The balanced differential amplifier has a first single-ended differential amplifier coupled at a first negative differential input terminal to a first input signal through a feedback network also coupled to an output terminal of the first amplifier. The first amplifier is also coupled at a first positive differential input terminal to a second input signal through a first resistor and to a reference voltage. The balanced differential amplifier also has a second single-ended differential amplifier coupled at a second negative differential input terminal to the second input signal through a second feedback network also coupled to an output terminal of the second amplifier. The second amplifier is also coupled at a second positive differential input terminal to the first input signal through a second resistor and to the reference voltage.