Abstract: A capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one dielectric layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: A capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one dielectric layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: An MOM capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one oxide layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: A signal generating apparatus includes: a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: An MOM capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one oxide layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: A phase locked loop (PLL) directly uses a charge pump and loop filter therein for fast and low-costly calibration. The PLL comprises a charge pump, a loop filter, a voltage comparator, a counting device, and a calibration device. The loop filter comprises a voltage storage device coupled to the charge pump for charging by the charge pump, wherein the voltage storage device comprises a variable impedance. The voltage comparator is coupled to a voltage reference and to the voltage storage device for comparing a voltage of the storage device and a voltage of the voltage reference. The counting device is coupled to the voltage comparator to measure the charge time required for the voltage of the voltage storage device to substantially equal to the voltage of the voltage reference. The calibration device adjusts the variable impedance to adjust the time measured by the counting device to a desired time.

Abstract: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a phase-locked loop device for generating a synthesized signal, wherein the phase-locked loop device includes a phase detector, a charge pump device, a filtering device, a controllable oscillator, and a switch device coupled to the controllable oscillator for selectively coupling the controllable oscillator to the filtering device or a tuning reference signal; a calibration controller generates a tuning reference signal and controls the switch device; and a first calibrator tunes the controllable oscillator into a predetermined sub-band according to a reference oscillating signal and a synthesized signal when the switch device couples the controllable oscillator to the tuning reference signal of the calibration controller.

Abstract: A device, having temperature compensation, includes a constant voltage provider for providing a constant voltage; and a compensating load coupled to the constant voltage provider for providing a resistive load to transform the constant voltage into a substantially constant current. The compensating load contains a resistor, having a negative temperature coefficient and coupled to the constant voltage; and a compensating unit, having a positive temperature coefficient and coupled in series to the resistor, for compensating a resistance variation of the resistor for a temperature variation.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.

Abstract: A tunable capacitance unit coupled between a pair of circuit nodes. The tunable capacitance unit comprises a tuning input supplying a tuning voltage, and first and second tuning capacitance units. Each of the tuning capacitance units comprises a pair of accumulation-mode MOS varactors with source/drains thereof coupled to the tuning input, a pair of blocking capacitors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective one of the circuit nodes, and a pair of biasing resistors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective bias terminal receiving a respective reference voltage. The reference voltages received by the first and second tuning capacitance units are symmetrical to a predetermined voltage.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.

Abstract: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.

Abstract: A device, having temperature compensation, includes a constant voltage provider for providing a constant voltage; and a compensating load coupled to the constant voltage provider for providing a resistive load to transform the constant voltage into a substantially constant current. The compensating load contains a resistor, having a negative temperature coefficient and coupled to the constant voltage; and a compensating unit, having a positive temperature coefficient and coupled in series to the resistor, for compensating a resistance variation of the resistor for a temperature variation.

Abstract: The present invention provides a charge pump in a phase lock loop circuit. The phase lock loop circuit comprises a voltage controlled oscillator (VCO) for producing a variable frequency output signal in response to a VCO control voltage. The charge pump comprises a current generating module for providing a first current, a second circuit for providing a bias current according to a bias control signal, a current mirror circuit that comprises a first current generating unit for generating a third current proportional to a sum of the first current and the second current, and a second current generating unit for generating a fourth current proportional to the sum of the first current and the second current, a first switch for sourcing the third current according to a first control signal and a second switch for sinking the fourth current according to a second control signal.

Abstract: In a symmetric crossover structure of two lines formed of a lower conductor layer and a higher conductor layer above a substrate, each of the two lines is branched to two routes at where they are crossed over to each other. The first route of the first line uses the higher layer to cross the first route of the second line and the lower layer to cross over the second route of the second line. The second route of the first line uses the lower layer to cross over the first route of the second line and the higher layer to cross over the second route of the second line. The two lines therefore have symmetric coupling effects to the substrate.