Patents by Inventor Tsing Hsu
Tsing Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742840Abstract: Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for example, generate a voltage mode signal (VMS) relative to CRP1 and representing an output parameter of a power supply circuit (PSC), and convert the VMS into a first CMS (CMS1). The control circuit may, for example, generate a control signal for the PSC from CMS1. Various embodiments may advantageously attenuate a noise margin of a CMS presented at the control circuit by a factor of at least 10 relative to an equivalent VMS.Type: GrantFiled: May 6, 2022Date of Patent: August 29, 2023Assignee: Alpha and Omega Semiconductor International LPInventors: Richard Schmitz, Tsing Hsu
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Publication number: 20220352881Abstract: Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for example, generate a voltage mode signal (VMS) relative to CRP1 and representing an output parameter of a power supply circuit (PSC), and convert the VMS into a first CMS (CMS1). The control circuit may, for example, generate a control signal for the PSC from CMS1. Various embodiments may advantageously attenuate a noise margin of a CMS presented at the control circuit by a factor of at least 10 relative to an equivalent VMS.Type: ApplicationFiled: May 6, 2022Publication date: November 3, 2022Applicant: Alpha and Omega Semiconductor International LPInventors: Richard Schmitz, Tsing Hsu
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Patent number: 11368144Abstract: Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for example, generate a voltage mode signal (VMS) relative to CRP1 and representing an output parameter of a power supply circuit (PSC), and convert the VMS into a first CMS (CMS1). The control circuit may, for example, generate a control signal for the PSC from CMS1. Various embodiments may advantageously attenuate a noise margin of a CMS presented at the control circuit by a factor of at least 10 relative to an equivalent VMS.Type: GrantFiled: April 30, 2021Date of Patent: June 21, 2022Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Richard Schmitz, Tsing Hsu
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Patent number: 9350245Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.Type: GrantFiled: March 21, 2015Date of Patent: May 24, 2016Assignee: Active-Semi, Inc.Inventors: Steven Huynh, Tsing Hsu
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Publication number: 20150194893Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.Type: ApplicationFiled: March 21, 2015Publication date: July 9, 2015Inventors: Steven Huynh, Tsing Hsu
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Patent number: 9000702Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.Type: GrantFiled: November 5, 2012Date of Patent: April 7, 2015Assignee: Active-Semi, Inc.Inventors: Steven Huynh, Tsing Hsu
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Publication number: 20140125266Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: Active-Semi, Inc.Inventors: Steven Huynh, Tsing Hsu
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Patent number: 8558582Abstract: A packaged controller for closed-loop control applications includes two dies packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.Type: GrantFiled: June 11, 2013Date of Patent: October 15, 2013Assignee: Active-Semi, Inc.Inventor: Tsing Hsu
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Patent number: 8461879Abstract: A packaged controller for closed-loop control applications includes two dice packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.Type: GrantFiled: May 28, 2012Date of Patent: June 11, 2013Assignee: Active-Semi, Inc.Inventor: Tsing Hsu
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Patent number: 8421416Abstract: A battery charger and method for a rechargeable battery pack which includes various elements in series with the cells to be charged, including but not limited to current control FETs, a fuse, current sense resistor, and internal series impedance of the series connected cells to be charged. The charging current Ichg flowing through these series elements reduces the voltage applied to the cells, thus lengthening charging time. A compensation voltage Vcomp, which when added to the nominal charging voltage for the series connected cells overcomes these voltage drops, facilitates more efficient charging while avoiding over-voltage damage to the cells. Three voltages representing substantially all of the voltage drops reducing the charging voltage on the cells, are summed, and the result is a compensation voltage which is utilized to change the nominal charge voltage for the battery to overcome these voltage drops.Type: GrantFiled: April 15, 2009Date of Patent: April 16, 2013Assignee: Texas Instruments IncorporatedInventors: Tsing Hsu, Yevgen Barsukov, Robert Martinez, Peter Mignano
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Patent number: 8093941Abstract: Systems and devices for dynamically scaled charge pumping are presented. Example embodiments of the disclosed systems of dynamically scaled charge pumping enable regulation of the output voltage at a particular ratio and to dynamically control the ratio based on the input voltage. A charge pumping circuit is enabled by an oscillator. The charge pump oscillator is enabled by the output of a comparator. The comparator compares an input voltage to a comparator voltage, which is a divided version of the output voltage. The output voltage is referenced to a regulated voltage and the comparison voltage is divided between the two voltages by a resistor divider. The regulated voltage remains flat until the input voltage equals the reference voltage. At that point, the regulated voltage will begin to rise and follow the input voltage. Before the reference voltage is reached, the output voltage equals the input voltage multiplied by the resistor divider ratio.Type: GrantFiled: February 18, 2010Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Bradford Lawrence Hunter, Richard David Nicholson, Tsing Hsu
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Publication number: 20110089996Abstract: Systems and devices for dynamically scaled charge pumping are presented. Example embodiments of the disclosed systems of dynamically scaled charge pumping enable regulation of the output voltage at a particular ratio and to dynamically control the ratio based on the input voltage. A charge pumping circuit is enabled by an oscillator. The charge pump oscillator is enabled by the output of a comparator. The comparator compares an input voltage to a comparator voltage, which is a divided version of the output voltage. The output voltage is referenced to a regulated voltage and the comparison voltage is divided between the two voltages by a resistor divider. The regulated voltage remains flat until the input voltage equals the reference voltage. At that point, the regulated voltage will begin to rise and follow the input voltage. Before the reference voltage is reached, the output voltage equals the input voltage multiplied by the resistor divider ratio.Type: ApplicationFiled: February 18, 2010Publication date: April 21, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Bradford Lawrence Hunter, Richard David Nicho, Tsing Hsu
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Publication number: 20090261786Abstract: A battery charger and method for a rechargeable battery pack which includes various elements in series with the cells to be charged, including but not limited to current control FETs, a fuse, current sense resistor, and internal series impedance of the series connected cells to be charged. The charging current Ichg flowing through these series elements reduces the voltage applied to the cells, thus lengthening charging time. A compensation voltage Vcomp, which when added to the nominal charging voltage for the series connected cells overcomes these voltage drops, facilitates more efficient charging while avoiding over-voltage damage to the cells. Three voltages representing substantially all of the voltage drops reducing the charging voltage on the cells, are summed, and the result is a compensation voltage which is utilized to change the nominal charge voltage for the battery to overcome these voltage drops.Type: ApplicationFiled: April 15, 2009Publication date: October 22, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Tsing Hsu, Yevgen Barsukov, Robert Martinez, Peter Mignano