Patents by Inventor Tso-chun Tony Wang

Tso-chun Tony Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6613672
    Abstract: A process of fabricating a deep trench capacitor includes the steps of: depositing a nitride masking layer over a substrate; removing portions of the nitride masking layer and substrate to form an exposed deep trench having sidewalls and a bottom surface; forming an oxide fill plug to fill a bottom portion of the trench; removing the oxide fill plug from the trench; doping a region of the substrate enveloping the bottom portion of the trench; depositing a spacer insulating layer over the sidewalls and bottom surface of the trench; removing a portion of the spacer insulating layer to expose a central portion of the bottom surface of the trench; depositing a conducting layer over the spacer insulating layer, and the exposed central portion of the bottom surface, the conducting layer and the doped region of the substrate being in electrical contact and forming a first plate of the capacitor; removing a portion of the conducting layer; removing the spacer insulating layer to expose outer walls of the conducting l
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: September 2, 2003
    Assignee: Mosel Vitelic, Inc.
    Inventors: Tso-Chun Tony Wang, Houng-Chi Wei
  • Patent number: 6352908
    Abstract: A method of forming an isolation structure includes the steps of: providing a silicon substrate; forming an upper pad oxide layer superjacent a top surface of the substrate, and a lower pad oxide layer subjacent a bottom surface of the substrate; forming a nitride masking layer superjacent the upper pad oxide layer, and a lower pad silicon nitride layer subjacent the lower pad oxide layer; patterning and etching the nitride masking layer to expose a portion of the upper pad oxide layer; applying a first etching solution to the exposed portion of the upper pad oxide layer to expose a portion of the substrate substantially defining the boundaries of an active area, and simultaneously forming an undercut cavity by removing a portion of the upper pad oxide layer under the exposed edges of the nitride masking layer surrounding the exposed portion of the substrate; performing an oxidation process to form an etching stop layer over the exposed portion of the substrate and in the undercut cavity, the oxidation proces
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: March 5, 2002
    Assignee: Mosel Vitelic, Inc.
    Inventors: Wei-Sheng King, Tso-Chun Tony Wang
  • Patent number: 6251722
    Abstract: A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: June 26, 2001
    Assignee: Mosel Vitelic Inc.
    Inventors: Houng-chi Wei, Tso-chun Tony Wang