Patents by Inventor Tso-Hui Ting
Tso-Hui Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9780007Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.Type: GrantFiled: January 4, 2012Date of Patent: October 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xu Ouyang, Yunsheng Song, Tso-Hui Ting, Yongchun Xin
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Patent number: 9702930Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: GrantFiled: April 5, 2016Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 9524930Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.Type: GrantFiled: January 29, 2014Date of Patent: December 20, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
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Publication number: 20160216321Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 9354252Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: GrantFiled: December 4, 2014Date of Patent: May 31, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 9151781Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/NĂ—2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.Type: GrantFiled: February 16, 2012Date of Patent: October 6, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oleg Gluschenkov, Muthukumarasamy Karthikeyan, Yunsheng Song, Tso-Hui Ting, Richard P. Volant, Ping-Chuan Wang
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Publication number: 20150145544Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: ApplicationFiled: December 4, 2014Publication date: May 28, 2015Inventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 8963567Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: GrantFiled: October 31, 2011Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 8759152Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.Type: GrantFiled: June 6, 2012Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
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Patent number: 8742782Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.Type: GrantFiled: July 27, 2011Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Publication number: 20140145351Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.Type: ApplicationFiled: January 29, 2014Publication date: May 29, 2014Applicant: International Business Machines CorporationInventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
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Patent number: 8489225Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system.Type: GrantFiled: March 8, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Yongchun Xin, Xu Ouyang, Yunsheng Song, Tso-Hui Ting
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Publication number: 20130169308Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xu Ouyang, Yunsheng Song, Tso-Hui Ting, Yongchun Xin
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Publication number: 20130106455Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 8429193Abstract: A system and a method are provided. The method includes assigning an entity to a ticket group associated with an ID thereof, displaying to the entity reports, which are each organized with an associated security access control, in accordance with the ticket group, determining whether the entity is authorized to access any selected one or more of the reports in accordance with a result of a comparison between an access level associated with the entity ID and the security access control associated with each of the one or more of the stored reports, and granting or denying the access in accordance with the determination.Type: GrantFiled: January 9, 2009Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Yunsheng Song, Tso-Hui Ting, Brian M. Trapp
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Publication number: 20130027051Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 8299809Abstract: An apparatus is provided and includes a thermally isolated device under test to which first and second voltages are sequentially applied, a local heating element to impart first and second temperatures to the device under test substantially simultaneously while the first and second voltages are sequentially applied, respectively and a temperature-sensing unit to measure the temperature of the device under test.Type: GrantFiled: September 21, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Tso-Hui Ting, Ping-Chuan Wang, Mohammed I. Younus
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Publication number: 20120241977Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.Type: ApplicationFiled: June 6, 2012Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
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Publication number: 20120232686Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: International Business Machines CorporationInventors: Yongchun Xin, Xu Ouyang, Yunsheng Song, Tso-Hui Ting
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Patent number: 8237278Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.Type: GrantFiled: November 16, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang