Patents by Inventor Tso-Jung Chang

Tso-Jung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079392
    Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung Chang, Jeng-Shien Hsieh, Shih-Ping Lin, Chih-Peng Lin, Chieh-Yen Chen, Chen-Hua Yu
  • Publication number: 20240047365
    Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure and a second chip structure over a carrier substrate. The method also includes forming an interconnection structure directly over and contacting the first chip structure and the second chip structure. The interconnection structure has multiple dielectric layers and multiple conductive features. One of the conductive features extends across a first edge of the first chip structure and a second edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure. The method further includes directly bonding a third chip structure to the interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
    Type: Application
    Filed: January 5, 2023
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Jeng-Shien HSIEH, Shih-Ping LIN, Chieh-Yen CHEN, Chen-Hua YU
  • Publication number: 20150305068
    Abstract: In a device and a method for communication back end processing based on user end dynamic feedback to configure communication linking, the communication back end processing device includes a communication module and an optimization configuration module. The communication module communicates with a plurality of external base stations, one of base stations communicates with an external user end. The optimization configuration module is electrically connected to the communication module and triggers the user end to transmit user information to the optimization configuration module. The optimization configuration module triggers the base station to transmit the base station information to the optimization configuration module. The optimization configuration module according to user information and at least one piece of base station information assigns a base station to connect the user end, so as to optimize the communication linking status between assigned base station and user end.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Applicant: Yuan Ze University
    Inventors: Heng-Tung Hsu, Tso-Jung Chang