Patents by Inventor Tso-Min Chou

Tso-Min Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10256294
    Abstract: The present disclosure relates to a vertical gallium-nitride (GaN) power field-effect transistor (FET) with a field plate structure. The vertical GaN power FET includes a conductive substrate, a drift region, a field plate structure, a channel region with tapered side walls, a gate dielectric region, a gate contact, a drain contact and source contacts. The field plate structure includes a lower layer formed of pi p-type graded AlGaN and a upper layer formed of p-type GaN. The field plate structure utilizes the charge separation at the interface between the lower layer and the upper layer to achieve high breakdown voltage.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 9, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Subrahmanyam V. Pilla, Tso-Min Chou
  • Publication number: 20160343801
    Abstract: The present disclosure relates to a vertical gallium-nitride (GaN) power field-effect transistor (FET) with a field plate structure. The vertical GaN power FET includes a conductive substrate, a drift region, a field plate structure, a channel region with tapered side walls, a gate dielectric region, a gate contact, a drain contact and source contacts. The field plate structure includes a lower layer formed of pi p-type graded AlGaN and a upper layer formed of p-type GaN. The field plate structure utilizes the charge separation at the interface between the lower layer and the upper layer to achieve high breakdown voltage.
    Type: Application
    Filed: February 25, 2016
    Publication date: November 24, 2016
    Inventors: Subrahmanyam V. Pilla, Tso-Min Chou