Abstract: Methods and apparatus for programming a ferroelectric memory according to various desired and constraining characteristics, such as the retention of the data written to the memory, the endurance of the memory itself, both retention and endurance, power consumption, constraints on available voltage levels, etc. The characteristics of the signal used to write the data to memory (e.g., voltage, power, etc.) are selected to as to satisfy the various desired and constraining characteristics.

Abstract: Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Abstract: Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.

Abstract: Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement circuitry include memory cells, memory arrays, and/or other logic-based circuitry. For example, in exemplary embodiments, 3D FeFET AND memory arrays with vertical and horizontal channel structures are provided.

Abstract: Methods and apparatus for programming a ferroelectric memory according to various desired and constraining characteristics, such as the retention of the data written to the memory, the endurance of the memory itself, both retention and endurance, power consumption, constraints on available voltage levels, etc. The characteristics of the signal used to write the data to memory (e.g., voltage, power, etc.) are selected to as to satisfy the various desired and constraining characteristics.

Abstract: Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.

Abstract: Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Abstract: Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement circuitry include memory cells, memory arrays, and/or other logic-based circuitry. For example, in exemplary embodiments, 3D FeFET AND memory arrays with vertical and horizontal channel structures are provided.

Abstract: Improvements in Complementary Metal Oxide Semiconductor (CMOS) devices; in particular, field effect transistors (FETs) and devices using said transistors which are able to take advantage of the higher carrier mobility of electrons compared to holes by replacing the conventional p-channel transistor with an n-channel transistor having a double gate (or vice versa): Such a. Unipolar CMOS (U-CMOS) transistor can be realized by adapting the source and/or the drain such that when the body region undergoes inversion at a first surface current, is able to flow between the drain and the source and when the body region undergoes inversion at a second surface current is not able to flow between the drain and the source. Various logic gates may be constructed using U-CMOS transistors.

Abstract: Improvements in Complementary Metal Oxide Semiconductor (CMOS) devices; in particular, field effect transistors (FETs) and devices using said transistors which are able to take advantage of the higher carrier mobility of electrons compared to holes by replacing the conventional p-channel transistor with an n-channel transistor having a double gate (or vice versa): Such a Unipolar CMOS (U-CMOS) transistor can be realised by adapting the source and/or the drain such that when the body region undergoes inversion at a first surface current, is able to flow between the drain and the source and when the body region undergoes inversion at a second surface current is not able to flow between the drain and the source. Various logic gates may be constructed using U-CMOS transistors.

Abstract: A memory including an array of memory cells, each of which includes a ferroelectric field effect transistor (FET) as its memory element; and sense and refresh circuitry connected to the array of memory cells to read stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and to refresh the stored data.

Abstract: A semiconductor structure including a single-crystal region composed of an isotopically enriched material, wherein the isotopically enriched material is selected from a subset consisting of all semiconductor materials except elemental silicon; and a semiconductor device formed by using said isotopically enriched semiconductor region.

Abstract: A semiconductor structure including a single-crystal region composed of an isotopically enriched semiconductor material, and a semiconductor device formed in the isotopically enriched semiconductor region.

Abstract: The electrical properties of MIS semiconductor devices, which have been damaged by radiation, are restored by treating the devices in a properly oriented RF field at low pressure.