Abstract: A power semiconductor including a gate, a source, a plurality of first long-strip source metal layer, a drain and a plurality of second long-strip drain metal layer is provided. The source includes a first copper particle layer and a first metal layer that covers the bottom surface of the first copper particle layer. The source is bonded to the first long-strip source metal layer via a first metal pillar. The drain includes a second copper particle layer and a second metal layer that covers the bottom surface of the second copper particle layer. The drain is bonded to the second long-strip drain metal layer via a second metal pillar. The thickness of the first copper particle layer and the second copper particle layer are 5 ?m˜100 ?m. The first copper particle layer and the second copper particle layer are formed by plating and stacking a plurality of large-grain copper.

Abstract: A power semiconductor including a gate, a source, a plurality of first long-strip source metal layer, a drain and a plurality of second long-strip drain metal layer is provided. The source includes a first copper particle layer and a first metal layer that covers the bottom surface of the first copper particle layer. The source is bonded to the first long-strip source metal layer via a first metal pillar. The drain includes a second copper particle layer and a second metal layer that covers the bottom surface of the second copper particle layer. The drain is bonded to the second long-strip drain metal layer via a second metal pillar. The thickness of the first copper particle layer and the second copper particle layer are 5 ?m˜100 ?m. The first copper particle layer and the second copper particle layer are formed by plating and stacking a plurality of large-grain copper.

Abstract: A power semiconductor is provided. The power semiconductor includes a gate, a source, a silicon chip and a drain. The source includes a first copper particle layer and a first metal layer. The first copper particle layer covers the upper surface of the first metal layer. The silicon chip is bonded to the lower surface of the first metal layer. The drain is bonded to the lower surface of the silicon chip. The thickness of the first copper particle layer is greater than the thickness of the first metal layer. All copper mentioned are of large grain copper with size greater than 0.25 um.

Abstract: A power semiconductor is provided. The power semiconductor includes a gate, a source, a silicon chip and a drain. The source includes a first copper particle layer and a first metal layer. The first copper particle layer covers the upper surface of the first metal layer. The silicon chip is bonded to the lower surface of the first metal layer. The drain is bonded to the lower surface of the silicon chip. The thickness of the first copper particle layer is greater than the thickness of the first metal layer. All copper mentioned are of large grain copper with size greater than 0.25 um.

Abstract: A solar cell includes an N-type semiconductor, a P-type semiconductor, a top electrode and a bottom electrode. The P-type semiconductor is closely combined with the N-type semiconductor, and a PN junction is formed between the P-type semiconductor and the N-type semiconductor, and the P-type semiconductor includes at least a deep trench. The top electrode is connected to the N-type semiconductor, and the bottom electrode is connected to the P-type semiconductor, and the bottom electrode includes at least a microelectrode column embedded into the deep trench and electrically connected to the P-type semiconductor. When the P-type semiconductor has a diffusion length T, the distance between the PN junction and an upper end of the microelectrode column is not greater than ½T or half T.