Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then, another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer.

Abstract: A dual-bit nitride read only memory (NROM) cell is provided. The NROM cell includes a substrate. A first oxide-nitride-oxide (ONO) layer and a second ONO layer are positioned on the substrate respectively, the first ONO layer and the second ONO layer being separated by a predetermined region. A first control gate is positioned on the first ONO layer and a second control gate is positioned on the second ONO layer. A select gate is positioned on the substrate within the predetermined region. Two conductive areas are positioned in the substrate adjacent to the first ONO layer and the second ONO layer respectively, functioning as a source and a drain of the NROM cell.

Abstract: The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then, another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer.

Abstract: The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer.

Abstract: A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

Abstract: A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

Abstract: The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the device isolation structures and on the substrate where the sources are present. Drains are provided in the top layer of the substrate where the tunneling oxide layer is absent in between the device isolation structures. Polysilicon blocks are extended across the ends of two device isolating structures, above the tunnel oxide layer. A silicon oxide cap layer is located on the polysilicon block. The silicon oxide layers are formed on the sidewalls of the polysilicon blocks. The polysilicon layer is on the sidewall of the polysilicon blocks and the polysilicon blocks are separated by the silicon oxide layer. The silicon oxide layer covers the surface of the polysilicon layers.

Abstract: The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the device isolation structures and on the substrate where the sources are present. Drains are provided in the top layer of the substrate where the tunneling oxide layer is absent in between the device isolation structures. Polysilicon blocks are extended across the ends of two device isolating structures, above the tunnel oxide layer. A silicon oxide cap layer is located on the polysilicon block. The silicon oxide layers are formed on the sidewalls of the polysilicon blocks. The polysilicon layer is on the sidewall of the polysilicon blocks and the polysilicon blocks are separated by the silicon oxide layer. The silicon oxide layer covers the surface of the polysilicon layers.

Abstract: A method for forming self-aligned split gates in a flesh memory is disclosed. The method includes two-step lithographic definition of a split gate and nitride spacer formation of the gate. The two-step lithography procedure is designed to assist the nitride spacer formation. The nitride spacer formation is used to facilitate gate etching in a self-aligned manner so that the channel length of the split gate is under proper control and the effect of gate misalignment can be totally avoided. The product quality of the flesh memory therefore gets improved.

Abstract: A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.

Abstract: The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the device isolation structures and on the substrate where the sources are present. Drains are provided in the top layer of the substrate where the tunneling oxide layer is absent in between the device isolation structures. Polysilicon blocks are extended across the ends of two device isolating structures, above the tunnel oxide layer. A silicon oxide cap layer is located on the polysilicon block. The silicon oxide layers are formed on the sidewalls of the polysilicon blocks. The polysilicon layer is on the sidewall of the polysilicon blocks and the polysilicon blocks are separated by the silicon oxide layer. The silicon oxide layer covers the surface of the polysilicon layers.

Abstract: A semiconductor wafer is provided having a substrate, and a tunneling oxide layer is formed thereon. A sacrificial layer defining an active region is formed over the tunneling oxide layer, and a defined first polysilicon layer is formed on the tunneling oxide layer within the active region and covered by the sacrificial layer.

Abstract: A method of manufacturing a self-aligned split-gate flash memory cell with high coupling ratio is disclosed. A polysilicon spacer is first formed on each of the inner walls between the two select gates on which a dielectric layer is formed. A drain and a source are next formed adjacent to each of the outer walls of the two select gates and between the two polysilicon spacers, respectively. A silicon oxide layer is deposited. A predetermined thickness of the silicon oxide layer is then removed and the dielectric layer is removed down to a predetermined thickness by using a dry etching process. Finally, a control gate is formed above the polysilicon spacers.

Abstract: A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.