Abstract: A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells.

Abstract: A method for forming shallow trench isolation (STI) structures on a semiconductor substrate is disclosed. First a semiconductor substrate with a first area and a second area adjacent to the first area is provided. A mask layer is formed on the substrate, and is etched to expose portions of the substrate. A first photoresist is formed to cover the second area for exposing the first area. A first implanting procedure is performed with a titled angle to form first doping areas on the substrate encroaching into portions of the substrate covered by the first photoresist. The first photoresist is removed. A second photoresist is formed on the substrate to cover the first area for exposing the second area. And a second implanting procedure is done with a titled angle to form second doping areas on the substrate encroaching into portions of the substrate covered by the second photoresist. The second photoresist is removed.